US 2026/0305325 A1Published application

Back-end-of-line passive device structure

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsTsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen

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Abstract

A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.

Claims20

Dependent claims

A device structure, comprising:

a first conductor plate layer;
a second conductor plate layer disposed over the first conductor plate layer;
a third conductor plate layer disposed over the second conductor plate layer;
a fourth conductor plate layer disposed over the third conductor plate layer;
and
a fifth conductor plate layer disposed over the fourth conductor plate layer,
wherein a vertical projection area of an outer edge of the second conductor plate layer falls completely within a vertical projection area of an outer edge of the first conductor plate layer,
wherein a vertical projection area of an outer edge of the fourth conductor plate layer falls completely within a vertical projection area of an outer edge of the third conductor plate layer,
wherein a vertical projection area of an outer edge of the fifth conductor plate layer encloses the vertical projection area of the outer edge of the fourth conductor plate layer.

6 more elements

A device structure, comprising:

a contact feature disposed in a first dielectric layer;
a second dielectric layer over the contact feature and the first dielectric layer;
a metal-insulator-metal (MIM) structure disposed over the second dielectric layer;
and
a third dielectric layer over the MIM structure,
wherein the MIM structure comprises:
a first dummy plate over the second dielectric layer,
a second dummy plate over the first dummy plate,
a third dummy plate over the second dummy plate, and
a fourth dummy plate over the third dummy plate,
wherein an area of the second dummy plate is greater than an area of the first dummy plate,
wherein an area of the fourth dummy plate is greater than an area of the third dummy plate.

9 more elements

A device structure, comprising:

a first conductor plate layer;
a first dummy plate spaced apart from the first conductor plate layer by a spacing S;
a second conductor plate layer over the first conductor plate layer;
a third conductor plate layer over the second conductor plate layer;
a second dummy plate over the first dummy plate and spaced apart from the third conductor plate layer by the spacing S;
a fourth conductor plate layer over the third conductor plate layer;
a third dummy plate over the second dummy plate and spaced apart from the fourth conductor plate layer by the spacing S;
a fifth conductor plate layer over the fourth conductor plate layer;
and
a fourth dummy plate over the third dummy plate and spaced apart from the fifth conductor plate layer by the spacing S,
wherein a vertical projection area of an outer edge of the second conductor plate layer falls completely within a vertical projection area of an outer edge of the first conductor plate layer,
wherein a vertical projection area of an outer edge of the fourth conductor plate layer falls completely within a vertical projection area of an outer edge of the third conductor plate layer,
wherein a vertical projection area of an outer edge of the fifth conductor plate layer encloses the vertical projection area of the outer edge of the fourth conductor plate layer,
wherein an area of the second dummy plate is greater than an area of the first dummy plate,
wherein an area of the fourth dummy plate is greater than an area of the third dummy plate.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/706,217Filed 12 Jun 2026
Priority: 3 Dec 2021
Published: 1 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10W 20/496
Capacitive arrangements or effects of, or between wiring layers: capacitor integral with wiring layers
H10D 1/696
Electrodes: comprising multiple layers, e.g. comprising a barrier layer and a metal layer
H10D 1/714
Having non-planar surfaces, e.g. formed by texturisation: having horizontal extensions
H10D 1/716
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions

Family

Application63/285,820Us provisional application · filed 3 Dec 2021
Application17/586,287Division · filed 27 Jan 2022
Application18/447,722Continuation · filed 10 Aug 2023
Application18/784,616Continuation · filed 25 Jul 2024
Application19/706,217Continuation
Application18/447,722Division
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From the US filing history. Foreign family members aren’t listed.