Voltage differential tolerant net lines in semiconductor structures

A semiconductor structure comprising:

• a first wiring layer comprising a first metal wire, the first metal wire being a first voltage net structure and having a recess defined therein;
• a second wiring layer comprising:
• a second metal wire, the second metal wire being a second voltage net structure, wherein the second metal wire is opposite a non-recessed portion of the first metal wire;
• and
• a third metal wire, the third metal wire being a third voltage net structure, wherein the third metal wire is opposite a recessed portion of the first metal wire,
• wherein a distance between the third metal wire and the recessed portion of the first metal wire is greater than a distance between the second metal wire and the non-recessed portion of the first metal wire;
• an interlayer dielectric (ILD) separating the first wiring layer from the second wiring layer and the second metal wire from the third metal wire;
• and
• a capping layer separating the first metal wire of the first wiring layer from the ILD,
• wherein a voltage differential tolerance between the first metal wire and the third metal wire is greater than a voltage differential tolerance between the first metal wire and the second metal wire based on resistance to time-dependent dielectric breakdown (TDDB).

A method of forming a semiconductor structure comprising the steps of:

• forming a first wiring layer comprising a first metal wire, the first metal wire being a first voltage net structure;
• etching a recess in the first metal wire;
• depositing a capping layer over the first metal wire and the recess of the first metal wire;
• depositing an interlayer dielectric (ILD) on the capping layer;
• and
• forming a second wiring layer in the ILD, wherein forming the second wiring layer comprises:
• depositing a hard mask on the ILD and etching, within the ILD, a plurality of wiring patterns, wherein a first wiring pattern of the plurality of wiring patterns is etched opposite a non-recessed portion of the first metal wire and a second wiring pattern of the plurality wiring patterns is etched opposite a recessed portion of the first metal wire;
• filling the first wiring pattern to form a second metal wire of the semiconductor structure, the second metal wire being a second voltage net structure;
• and
• filling the second wiring pattern to form a third metal wire of the semiconductor structure, the third metal wire being a third voltage net structure;
• wherein the steps are carried out such that, subsequent to filling the second wiring pattern, the semiconductor structure is configured such that:
• a first voltage differential tolerance is provided between the first voltage net structure and the second voltage net structure;
• a second voltage differential tolerance is provided between the first voltage net structure and the third voltage net structure;
• and
• the second voltage differential tolerance is greater than the first voltage differential tolerance based on resistance to time-dependent dielectric breakdown (TDDB).