Method for manufacturing a system-on-chip including quantum dot regions and mos transistors
AssigneeSTMicroelectronics International N.V.
InventorCarlos Augusto SUAREZ SEGOVIA
Life of this patent
Estimating the term…
Abstract
Gate structures are manufactured over a semiconductor layer in a first circuit part adapted to locate regions of quantum dots and in a second circuit part for transistors. A first stop layer is formed in the first circuit part but not the second circuit part. A second stop layer is formed in the first circuit part and in the second circuit part. Metal contacts are formed that vertically pass through the second stop layer and stop at an end located in or on the first stop layer in the first circuit part, and that vertically pass through the second stop layer and stop at an end located in or on the gate structures in the second circuit part.
Claims16
A system-on-chip, including:
- a first circuit part including regions of quantum dots located in a semiconductor layer facing first gate structures;
- a second circuit part including transistors provided with second gate structures;
- wherein the first gate structures are covered by a stack of a first stop layer and a second stop layer;
- wherein the second gate structures are covered by the second stop layer but not the first stop layer;
- wherein the first stop layer is configured to apply a first stress in a first direction;
- wherein the second stop layer is configured to apply a second stress in the first direction;
- first metal contacts for the first circuit part that vertically pass through the second stop layer and stop at an end located in or on the first stop layer;
- and
- second metal contacts for the second circuit part that vertically pass through the second stop layer and stopping at an end located in or on the second gate structures.
A method for manufacturing a system-on-chip, comprising:
- manufacturing, in a first circuit part, first gate structures over a semiconductor layer configured to locate regions of quantum dots facing the first gate structures;
- manufacturing, in a second circuit part, second gate structures of transistors over the semiconductor layer;
- forming a first stop layer covering the first gate structures in the first circuit part but not covering the second gate structures in the second circuit part;
- forming a second stop layer covering the first stop layer in the first circuit part and covering the second gate structures in the second circuit part;
- wherein the first stop layer is configured to apply a first stress in a first direction;
- wherein the second stop layer is configured to apply a second stress in the first direction;
- forming first metal contacts vertically passing through the second stop layer and stopping at an end located in or on the first stop layer in the first circuit part;
- and
- forming second metal contacts vertically passing through the first stop layer and stopping at an end located in or on the second gate structures in the second circuit part.
Dependencies are inferred from the claim text.