Semiconductor layout pattern with offset metal layer and manufacturing method thereof

A semiconductor layout pattern, comprising:

• a first metal layer comprising a plurality of fishbone line patterns, wherein each of the plurality of fishbone line patterns comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction;
• a second metal layer disposed on the first metal layer, the second metal layer comprising a plurality of second patterns;
• and
• a plurality of magnetic tunnel junction (MTJ) elements respectively disposed on the plurality of second patterns,
• wherein, with respect to any one of the plurality of fishbone line patterns, the plurality of second patterns located on a first side of the principal axis pattern of said fishbone line pattern and the second patterns located on a second side of the principal axis pattern of said fishbone line pattern are offset from each other along the second direction;
• and
• wherein, with respect to two adjacent fishbone line patterns of the plurality of fishbone line patterns, the second patterns located on a same side relative to said two adjacent fishbone line patterns are aligned with each other along the second direction.