Tub forksheet and cfet architectures for reduced spacing of complementary transistors

An apparatus, comprising:

• a dielectric spine between and in contact with a first stack of first nanoribbons and a second stack of second nanoribbons;
• a first gate structure between the dielectric spine and a first dielectric wall, the first stack of first nanoribbons through the first gate structure in a first transistor structure, the first gate structure comprising a first dielectric layer on the dielectric spine and the first dielectric wall and between a pair of the first nanoribbons;
• and
• a second gate structure between the dielectric spine and a second dielectric wall, the second stack of second nanoribbons through the second gate structure in a second transistor structure, the second gate structure comprising a second dielectric layer on the dielectric spine and the second dielectric wall and between a pair of the second nanoribbons.

A method, comprising:

• forming a first dielectric wall between a first stack of first nanoribbons and a second stack of second nanoribbons, the first stack of first nanoribbons on a second dielectric wall, the second stack of second nanoribbons on a third dielectric wall, the first and second stacks of first and second nanoribbons between the second and third dielectric walls, the first dielectric wall between the first and second stacks of first and second nanoribbons;
• opening a cavity between the first and second dielectric walls;
• forming a dielectric stack on the first nanoribbons;
• and
• forming a gate electrode over the first stack of first nanoribbons.