Integrated circuit structures having hybrid spine-fet architecture

An integrated circuit structure, comprising:

• a spine field effect transistor (SFET) comprising a hybrid dielectric spine, the hybrid dielectric spine comprising:
• a gate region dielectric spine;
• and
• a source or drain region dielectric spine separate and distinct from the gate region dielectric spine.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first dielectric backbone along a direction;
• a first vertical stack of nanowires laterally adjacent to and in contact with a first side of the first dielectric backbone;
• a first gate stack around the first vertical stack of nanowires, the first gate stack in contact with the first side of the first dielectric backbone;
• a second vertical stack of nanowires laterally adjacent to and in contact a second side of the first dielectric backbone, the second side laterally opposite the first side;
• a second gate stack around the second vertical stack of nanowires, the second gate stack in contact with the second side of the first dielectric backbone;
• a second dielectric backbone along the direction;
• a first epitaxial source or drain structure at an end of the first vertical stack of nanowires, the first epitaxial source or drain structure laterally adjacent to and in contact with a first side of the second dielectric backbone;
• and
• a second epitaxial source or drain structure at an end of the second vertical stack of nanowires, the second epitaxial source or drain structure laterally adjacent to and in contact with a second side of the second dielectric backbone, the second side laterally opposite the first side.