Multi-gate devices with reduced parasitic capacitance and methods of forming the same

A method, comprising:

• forming an active region over a substrate and extending lengthwise along a first direction;
• forming an isolation feature over the substrate and alongside the active region;
• forming a source/drain feature over the active region, wherein a portion of the source/drain feature overhangs the isolation feature along a second direction different from the first direction, and wherein a top portion of the source/drain feature is above a top surface of a channel region of the active region;
• forming a gate structure comprising a gate dielectric layer over the active region and a gate electrode over the gate dielectric layer, wherein the gate electrode comprises a titanium-containing material;
• converting a portion of the source/drain feature into a dielectric layer;
• and
• after the converting, forming a source/drain contact electrically coupled to the source/drain feature.

A semiconductor device, comprising:

• an active region comprising a channel region and a source/drain region adjacent to the channel region;
• a gate structure over the channel region;
• a gate spacer disposed along a sidewall of the gate structure;
• a source/drain feature over the source/drain region;
• a contact etch stop layer (CESL) over the source/drain feature;
• an interlayer dielectric (ILD) layer over the CESL;
• a source/drain contact extending through the ILD layer and the CESL;
• and
• a dielectric layer disposed vertically between the source/drain feature and the CESL,
• wherein the source/drain contact is spaced apart from the gate structure by the CESL, the dielectric layer, and the gate spacer.