US 2026/0304923 A1 · CHANNEL WIDTH AND QUANTITY VARIATION IN GATE-ALL-AROUND AND FORKSHEET TRANSISTORS

Abstract

Techniques to form gate-all-around (GAA) and/or forksheet semiconductor devices that have varying semiconductor channel widths and varying numbers of semiconductor channel bodies (e.g., nanoribbons, nanosheets, nanowires). The techniques can be used in any number of transistor technologies, but are particularly useful in vertically stacked transistor configurations (e.g., stacked in a vertical z-direction from the substrate surface) and/or configurations that extend laterally in a horizontal x-or-y-direction). In an example, the n-channel device and the p-channel device may both be GAA or forksheet transistors each having any number of channel bodies extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Any number of adjacent devices may be patterned from a single fin to include varying channel body widths. In addition, any of the devices may include different numbers of channel bodies extending between corresponding source or drain regions.

Claims20

Dependent claims

An integrated circuit comprising:

a first plurality of semiconductor bodies extending from a first source or drain region in a first direction, the first plurality of semiconductor bodies having a first width in a second direction different from the first direction;
a second plurality of semiconductor bodies extending from a second source or drain region in the first direction, the second plurality of semiconductor bodies having a second width in the second direction that is greater than the first width, and the second source or drain region being aligned with the first source or drain region along the first direction;
and
a first gate structure extending over the first plurality of semiconductor bodies in the second direction, and a second gate structure extending over the second plurality of semiconductor bodies in the second direction;
wherein a total number of bodies in the first plurality of semiconductor bodies is less than a total number of bodies in the second plurality of semiconductor bodies.

2 more elements

An electronic device, comprising:

a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having a first plurality of semiconductor nanoribbons extending from a first source or drain region to a second source or drain region in a first direction, the first plurality of semiconductor nanoribbons having a first width in a second direction different from the first direction, and a first gate structure extending over the first plurality of semiconductor nanoribbons in the second direction;
a second semiconductor device having a second plurality of semiconductor nanoribbons extending from a third source or drain region to a fourth source or drain region in the first direction, the second plurality of semiconductor nanoribbons having a second width in the second direction that is greater than the first width, and a second gate structure extending over the second plurality of semiconductor nanoribbons in the second direction;
wherein a total number of nanoribbons in the first plurality of semiconductor nanoribbons is less than a total number of nanoribbons in the second plurality of semiconductor nanoribbons.

1 more element

An integrated circuit comprising:

a first plurality of semiconductor nanoribbons extending from a first source or drain region in a first direction, the first plurality of semiconductor nanoribbons having a first width in a second direction different from the first direction;
a second plurality of semiconductor nanoribbons extending from a second source or drain region in the first direction, the second plurality of semiconductor nanoribbons having a second width in the second direction that is greater than the first width, and the second source or drain region being aligned with the first source or drain region along the first direction;
and
a dielectric structure extending along the second direction and arranged substantially equidistant between the first source or drain region and the second source or drain region along the first direction;
wherein a total number of nanoribbons in the first plurality of semiconductor nanoribbons is less than a total number of nanoribbons in the second plurality of semiconductor nanoribbons.

2 more elements

Dependencies are inferred from the claim text.

Channel width and quantity variation in gate-all-around and forksheet transistors

Life of this patent

Channel width and quantity variation in gate-all-around and forksheet transistors

Life of this patent

Abstract

Claims20