Transistor structure and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Cheng Chu, Chien-Hua Huang, Shu-Hong Ou
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Abstract
A transistor structure and a method of forming the same are provided. The transistor structure includes a gate electrode disposed in a dielectric layer of an interconnect structure, a high-k dielectric layer disposed on the gate electrode, a channel layer disposed on the high-k dielectric layer, an electrode disposed on and in contact with the channel layer, and a liner layer surrounding sidewalls of the electrode. The liner layer is spaced apart from the channel layer by the electrode. The liner layer has a resistivity higher than the electrode. The electrode includes a glue layer disposed on and in contact with the channel layer, and a metallic portion surrounded by the glue layer.
Claims20
A transistor structure, comprising:
- a gate electrode disposed in a dielectric layer of an interconnect structure;
- a high-k dielectric layer disposed on the gate electrode;
- a channel layer disposed on the high-k dielectric layer;
- an electrode disposed on and in contact with the channel layer;
- a liner layer surrounding sidewalls of the electrode, and spaced apart from the channel layer by the electrode, wherein the liner layer has a resistivity higher than the electrode,
- wherein the electrode comprises:
- a glue layer disposed on and in contact with the channel layer;
- and
- a metallic portion surrounded by the glue layer.
A transistor structure, comprising:
- a gate electrode disposed in an interconnect structure above a substrate;
- a channel layer disposed on the gate electrode;
- a high-k dielectric layer is sandwiched between the gate electrode and the channel layer;
- an electrode disposed on and in contact with the channel layer, and surrounded by a dielectric layer;
- a liner layer surrounding sidewalls of the electrode and sandwiched between the electrode and the dielectric layer, wherein the liner layer has a resistivity higher than the electrode,
- wherein the electrode comprises:
- a glue layer on the channel layer, covering a bottom surface of the liner layer, and in contact with the dielectric layer;
- and
- a metallic portion disposed on and surrounded by the glue layer.
A method of forming a transistor structure, comprising:
- forming a gate electrode disposed in a first dielectric layer of an interconnect structure;
- depositing a high-k dielectric layer on the gate electrode;
- depositing a channel layer on the high-k dielectric layer;
- depositing a second dielectric layer on the channel layer;
- etching the second dielectric layer to form an opening revealing the channel layer;
- depositing a sacrificial layer on the channel layer and a portion of sidewalls of the second dielectric layer at a bottom of the opening;
- depositing a liner layer on the sidewalls of the second dielectric layer, wherein the liner layer covers a portion of the sacrificial layer;
- removing the sacrificial layer to reveal the channel layer and the portion of the sidewalls of the second dielectric layer;
- depositing a glue layer on the channel layer, on the portion of the sidewalls of the second dielectric layer, and on the liner layer, wherein the liner layer is spaced apart from the channel layer by the glue layer;
- filling a metallic material in the opening;
- and
- removing excess portions of the glue layer and the metallic material to form an electrode comprising the glue layer and a metallic portion surrounded by the glue layer.
Dependencies are inferred from the claim text.