Standard cell architecture with frontside and backside power via connections

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising
• a first semiconductor device comprising a first semiconductor region extending from a first source or drain region in a first direction, and a first portion of a gate structure extending over the first semiconductor region in a second direction substantially orthogonal to the first direction;
• a second semiconductor device comprising a second semiconductor region extending from a second source or drain region in the first direction, and a second portion of the gate structure extending over the second semiconductor region in the second direction;
• a dielectric layer beneath the gate structure and beneath the first source or drain region and the second source or drain region;
• a dielectric fill adjacent to and between the first source or drain region and the second source or drain region along the second direction;
• a first conductive via extending through an entire height of the dielectric fill and the dielectric layer, and adjacent to the first source or drain region along the second direction;
• a second conductive via extending through an entire height of the dielectric fill and the dielectric layer, and adjacent to the second source or drain region along the second direction;
• a first backside conductive layer beneath the dielectric layer and contacting a bottom surface of the first conductive via;
• and
• a second backside conductive layer beneath the dielectric layer and contacting a bottom surface of the second conductive via.

An integrated circuit comprising:

• a standard unit cell having a first semiconductor device and a second semiconductor device, the standard unit cell having a layout that is repeated across at least a portion of the integrated circuit;
• wherein the first semiconductor device comprises a first semiconductor region extending from a first source or drain region to a second source or drain region in a first direction, and a first portion of a gate structure extending over the first semiconductor region in a second direction substantially orthogonal to the first direction;
• wherein the second semiconductor device comprises a second semiconductor region extending from a third source or drain region to a fourth source or drain region in the first direction, and a second portion of the gate structure extending over the second semiconductor region in the second direction;
• a first conductive via extending along the first direction and aligned along a first boundary of the standard unit cell, the first conductive via being adjacent to the first source or drain region along the second direction;
• and
• a second conductive via extending along the first direction and aligned along a second boundary of the standard unit cell, the second conductive via being adjacent to the second source or drain region along the second direction.