SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS

A semiconductor device structure comprising a lateral GaN (gallium nitride) power transistor comprising:

• a substrate comprising a device area of the transistor;
• a nitride semiconductor layer formed on the device area of the substrate, the nitride semiconductor layer comprising a GaN/AlGaN heterostructure defining active regions for a plurality of transistor sections of a multi-section transistor;
• in each section, source electrodes and drain electrodes formed on the active region, and gate electrodes running in channel regions between adjacent source and drain electrodes;
• a first level of on-chip metallization (M1), M1 being patterned to interconnect comprising define source fingers and gate fingers of each transistor section and a gate bus;
• for each section, the gate bus comprising a first portion formed on an inactive region along a first edge of the active region, and second portions of the gate bus extending from the first portion of the gate bus and formed on inactive regions between active regions of each section, the gate electrodes being interconnected to adjacent second portions of the gate bus;
• an overlying second level of on-chip metallization (M2), M2 being patterned to define for each section a contact structure comprising a drain pad and first and second source contact areas, in each section the drain pad extending laterally in a width direction over a central part of the active region, and the first and second source contact areas being located each side of the drain pad;
• the first and second source contact areas being interconnected to form a source bus which is routed over said inactive regions;
• an intermetal dielectric layer provided between the first and second level metallization M1 and M2;
• the drain pad being interconnected by conductive micro-vias through the intermetal dielectric layer to the drain fingers;
• and
• the source fingers being connected laterally to said first and second contact areas of the source bus.