Superjunction transistor device and method

A transistor device, comprising:

• a superjunction region comprising a plurality of first regions of a first doping type and a plurality of second regions of a second doping type complementary to the first doping type, the first regions and the second regions being arranged alternately in a lateral direction of a semiconductor body;
• a plurality of transistor cells each comprising a gate electrode arranged in a gate trench and dielectrically insulated from the semiconductor body by a gate dielectric, a source region, and a body region;
• and
• a trench electrode arrangement comprising a first trench electrode grid arranged in a grid-shaped trench of the semiconductor body and insulated from the semiconductor body by a dielectric layer,
• wherein the first trench electrode grid comprises:
• a plurality of first longitudinal electrodes spaced apart from each other in a first lateral direction of the semiconductor body;
• and
• a plurality of first connection electrodes each connecting two adjacent ones of the first longitudinal electrodes,
• wherein the gate electrodes of at least some of the transistor cells are formed by the first longitudinal electrodes of the trench electrode grid.