US 2026/0304854 A1Published application

Sic trench mosfet with trench bottom protection structure and method for manufacturing the same

AssigneePower Master Semiconductor Co., Ltd.

InventorsHong Ki KIM, Hyung Jin LEE

Life of this patent

Estimating the term…

Loading patent…

Abstract

The present disclosure relates to a SiC trench MOSFET having a trench bottom protection structure for preventing destruction of a trench bottom oxide by blocking concentration of an electric field at the trench bottom oxide while simplifying a manufacturing process. More specifically, the present disclosure relates to a SiC MOSFET comprising: a semiconductor layer of a first conductivity type; a gate trench formed on an upper surface of the semiconductor layer; a source well structure of a second conductivity type formed on the upper surface of the semiconductor layer at a predetermined distance from the gate trench; a body region of the second conductivity type formed on the upper surface between the gate trench and the source well structure; a source region of the first conductivity type formed on an upper surface of the body region; and a trench bottom protection structure provided at a bottom of the gate trench.

Claims10

Dependent claims

A SiC MOSFET comprising:

a semiconductor layer of a first conductivity type;
a gate trench formed on an upper surface of the semiconductor layer;
a source well structure of a second conductivity type formed on the upper surface of the semiconductor layer at a predetermined distance from the gate trench;
a body region of the second conductivity type formed on the upper surface between the gate trench and the source well structure;
a source region of the first conductivity type formed on an upper surface of the body region;
and
a trench bottom protection structure provided at a bottom of the gate trench, wherein the trench bottom protection structure comprises:
a first bottom protection structure forming a second conductivity type region formed to a predetermined depth downward from a bottom of the trench;
and
a second bottom protection structure having a shape surrounding the first bottom protection structure and forming a first conductivity type region, wherein the second bottom protection structure is provided in a hemispherical shape at the bottom of the trench, and the first bottom protection structure is inserted inside the hemispherical shape, such that a bottom and sides of the first bottom protection structure are surrounded by the second bottom protection structure, and wherein the second bottom protection structure is formed being confined to a region directly below the bottom of the trench, contacts at least a portion of the region below the bottom of the trench, and does not extend upward along an outer sidewall of the trench.

7 more elements

A method for manufacturing a SiC MOSFET, the method comprising:

forming a body region of a second conductivity type on an upper surface of a semiconductor layer of a first conductivity type;
forming a source region of the first conductivity type on an upper surface of the body region;
forming a gate trench on the upper surface of the semiconductor layer;
forming a source well structure of the second conductivity type on the upper surface of the semiconductor layer at a predetermined distance from the gate trench;
and
forming a trench bottom protection structure at a bottom of the formed gate trench, wherein the forming of the trench bottom protection structure comprises:
performing a first conductivity type implant on a bottom of the trench to form a second bottom protection structure;
filling an interior of the trench with Poly-Si;
etching the filled Poly-Si to form a spacer;
performing a second conductivity type implant on the bottom of the trench to form a first bottom protection structure;
additionally performing the first conductivity type implant to reinforce the second bottom protection structure;
and
removing the formed spacer.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/635,588Filed 31 Mar 2026
Priority: KR 10-2025-00424651 Apr 2025
Published: 1 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 62/105
For increasing or controlling the breakdown voltage of reverse-biased devices: by having particular doping profiles, shapes or arrangements of PN…
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes
H10D 30/668
Vertical dmos [vdmos] fets: having trench gate electrodes, e.g. UMOS transistors
H10D 62/8325
Being Group IV materials comprising two or more elements, e.g. SiGe: silicon carbide