Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Yen CHUANG, Katherine H. CHIANG
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Abstract
A semiconductor device includes a bottom gate electrode, a gate insulating layer, an active layer, a dielectric layer, two interfacial layers and two source/drain electrodes. The gate insulating layer is disposed between the bottom gate electrode and the active layer. The dielectric layer is disposed on the active layer and the two interfacial layers are formed in first and second portions (i.e., contact areas) of the active layer and between the two source/drain electrodes and the active layer. The source/drain electrodes are electrically connected to the active layer through the interfacial layers and a channel region is form between the two source/drain electrodes.
Claims20
A semiconductor device, comprising:
- a bottom gate electrode;
- a gate insulating layer disposed on the bottom gate electrode;
- an active layer disposed on the gate insulating layer, wherein the gate insulating layer is disposed between the bottom gate electrode and the active layer;
- a dielectric layer disposed on the active layer;
- two interfacial layers formed in first and second portions of the active layer and the first and second portions are separated by the dielectric layer;
- and
- two source/drain electrodes formed on the two interfacial layers respectively, wherein the two source/drain electrodes are electrically connected to the active layer through the interfacial layers respectively and a channel region is form between the two source/drain electrodes.
A method for manufacturing a semiconductor device, comprising:
- forming a bottom gate electrode, a gate insulating layer and an active layer in order from bottom to top;
- forming a dielectric layer on the active layer;
- etching a portion of the dielectric layer to form at least one opening to expose a portion of the active layer;
- forming a metal oxide layer on the exposed portion, and an interfacial layer between the active layer and the metal oxide layer being self-formed in the exposed portion;
- removing the metal oxide layer to expose the interfacial layer;
- and
- forming a source/drain electrode on the interfacial layer and the source/drain electrode being electrically connected to the active layer through the interfacial layer.
A transistor, comprising:
- a bottom gate electrode;
- a gate insulating layer disposed on the bottom gate electrode;
- an indium gallium zinc oxide (IGZO) layer disposed on the gate insulating layer, wherein the gate insulating layer is disposed between the bottom gate electrode and the IGZO layer;
- a first indium oxide layer formed in a first portion of the IGZO layer;
- and
- a first source/drain electrode formed on the first indium oxide layer, wherein the first source/drain electrode is electrically connected to the IGZO layer through the first indium oxide layer, and indium concentration of the first indium oxide layer is higher than indium concentration of the IGZO layer.
Dependencies are inferred from the claim text.