Device leakage and yield for cells

Abstract

A chip includes a first diffusion region extending in a first direction, a first active gate extending across the first diffusion region in a second direction perpendicular to the first direction, a second active gate extending across the first diffusion region in the second direction, and a first floating gate extending across the first diffusion region in the second direction, wherein the first floating gate is between the first active gate and the second active gate, and wherein the first diffusion region includes a first source/drain between the first active gate and the first floating gate, and a second source/drain between the first floating gate and the second active gate. The chip also includes a first interconnect extending over the first floating gate and coupled between the first source/drain to the second source/drain.

Dependencies are inferred from the claim text.