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US 2026/0304830 A1Published application
Semiconductor device
AssigneesDenso Corporation, Toyota Jidosha Kabushiki Kaisha, MIRISE Technologies Corporation
InventorRyota SUZUKI
Life of this patent
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Abstract
A semiconductor device includes lower guard rings and upper guard rings. An upper portion of each of the lower guard rings overlaps a lower portion of the corresponding upper guard ring. A lower inner peripheral surface of each of the lower guard rings is offset to one side in a predetermined direction with respect to an upper inner peripheral surface of the corresponding upper guard ring. A lower outer peripheral surface of each of the lower guard rings is offset to the one side in the predetermined direction with respect to an upper outer peripheral surface of the corresponding upper guard ring.
Claims12
A semiconductor device, comprising
- a semiconductor layer including an element region in which an element structure is formed and a termination region located around the element region, wherein
- the semiconductor layer located in the termination region includes:
- a drift region of a first conductivity;
- a plurality of lower guard rings of a second conductivity provided in a first depth range surrounded by the drift region;
- and
- a plurality of upper guard rings of the second conductivity provided in a second depth range different from the first depth range and surrounded by the drift region,
- the plurality of lower guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along a predetermined direction connecting the element region and the termination region,
- the plurality of upper guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along the predetermined direction,
- each of the plurality of lower guard rings has a lower inner peripheral surface facing the element region and a lower outer peripheral surface opposite to the lower inner peripheral surface,
- each of the plurality of upper guard rings has an upper inner peripheral surface facing the element region and an upper outer peripheral surface opposite to the upper inner peripheral surface,
- an upper portion of the first depth range overlaps a lower portion of the second depth range within a third depth range,
- the lower inner peripheral surface of each of the plurality of lower guard rings is offset to one side in the predetermined direction with respect to the upper inner peripheral surface of a corresponding one of the plurality of upper guard rings, and
- the lower outer peripheral surface of each of the plurality of lower guard rings is offset to the one side in the predetermined direction with respect to the upper outer peripheral surface of a corresponding one of the plurality of upper guard rings.
10 more elements
A semiconductor device, comprising
- a semiconductor layer including an element region in which an element structure is formed and a termination region located around the element region, wherein
- the semiconductor layer located in the termination region includes:
- a drift region of a first conductivity;
- a plurality of lower guard rings of a second conductivity provided in a first depth range surrounded by the drift region;
- and
- a plurality of upper guard rings of the second conductivity provided in a second depth range different from the first depth range and surrounded by the drift region,
- the plurality of lower guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along a predetermined direction connecting the element region and the termination region,
- the plurality of upper guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along the predetermined direction,
- each of the plurality of lower guard rings has a lower inner peripheral surface facing the element region and a lower outer peripheral surface opposite to the lower inner peripheral surface,
- each of the plurality of upper guard rings has an upper inner peripheral surface facing the element region and an upper outer peripheral surface opposite to the upper inner peripheral surface,
- an upper portion of each of the plurality of lower guard rings overlaps a lower portion of a corresponding one of the plurality of upper guard rings,
- the lower inner peripheral surface of each of the plurality of lower guard rings is offset to one side in the predetermined direction with respect to the upper inner peripheral surface of a corresponding one of the plurality of upper guard rings, and
- the lower outer peripheral surface of each of the plurality of lower guard rings is offset to the one side in the predetermined direction with respect to the upper outer peripheral surface of a corresponding one of the plurality of upper guard rings,
- wherein the drift region includes:
- a low concentration drift region;
- and
- a high concentration drift region having an impurity concentration of the first conductivity higher than that of the low concentration drift region, wherein
- the high concentration drift region is provided at an upper side of the low concentration drift region, and
- the high concentration drift region is disposed at least between the upper guard rings adjacent to each other in the predetermined direction,
- wherein the high concentration drift region is disposed between the lower guard rings adjacent to each other in the predetermined direction,
- wherein
- the high concentration drift region includes a lower layer, an intermediate layer, and an upper layer,
- the intermediate layer has an impurity concentration of the first conductivity lower than that of the lower layer and the upper layer, and
- the intermediate layer is located so as to include a depth range in which the first depth range and the second depth range overlap each other.
21 more elements
Dependencies are inferred from the claim text.