US 2026/0304809 A1Published application

Iii-v heterojunction bipolar transistor and its manufacturing method

AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives

InventorsHervé BOUTRY, Alexis DIVAY, Christophe DUBARRY

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Abstract

A heterojunction bipolar transistor comprising, on a silicon substrate: a layer made of a first III-V material, a first mesa structure on said layer, comprising a collector layer, with the basis of a second III-V material N conductivity, and a base layer, with the basis of the second III-V material having a P+ conductivity, and a second mesa structure comprising an emitter layer with the basis of the first III-V material having an N conductivity. The transistor further includes collector, base, and emitter contacts made of a conductor material, suitable for a metallurgy of the metal levels of a CMOS transistor-b grated circuit. The transistor further includes an encapsulation layer made of a dielectric material, covering the first and second mesa structures, and the collector, base, and emitter contacts made of a dielectric material, suitable for an insulation of the metal levels of the CMOS transistor-based integrated circuit.

Claims16

Dependent claims

A method for producing a heterojunction bipolar transistor, the method comprising:

providing a stack comprising, along a direction z, a silicon-based substrate, a first layer made of a first III-V material, having a first type of conductivity with a first N+ doping level,
forming, by epitaxy, on the first layer of a collector layer, with a basis of a second III-V material having the first type of conductivity with a second N doping level,
forming, by epitaxy, on the collector layer of a base layer, with a basis of a third III-V material having a second type of conductivity with a first P+ doping level,
forming, by epitaxy, on the base layer of a emitter layer, with a basis of a fourth III-V material having the first type of conductivity with a third N doping level,
a first mesa-form structuration of the collector and base layers, configured to form a first mesa structure having a dimension L1 along a direction y perpendicular to the direction z,
a second mesa-form structuration of the emitter layer, configured to form a second mesa structure having a dimension L2 less than the dimension L1 along the direction y,
forming a collector contact on the first layer, at the border of the first mesa structure,
forming a base contact on the base layer, at the border of the second mesa structure,
forming an emitter contact on the emitter layer, said collector, base, and emitter contacts being formed with a basis of an electrically conductive material, suitable for a metallurgy of the metal levels of a complementary metal-oxide-semiconductor (CMOS) transistor-based integrated circuit,
forming at least one encapsulation layer covering the first layer, the first and second mesa structure, and the collector, base and emitter contacts said encapsulation layer being formed with a basis of a dielectric material, suitable for an insulation of the metal levels of the CMOS transistor-based integrated circuit, and
planarizing the at least one encapsulation layer.

8 more elements

A heterojunction bipolar transistor comprising, in a stack along a direction z on a silicon-based substrate:

a first layer made of a first III-V material having a first type of conductivity with a first N+ doping level,
a first mesa structure on the first layer, comprising collector layer, with a basis of a second III-V material having the first type of conductivity with a second N doping level, and a base layer, with a basis of a third III-V material having a second type of conductivity with a first P+ doping level, and
a second mesa structure on the first mesa structure, comprising an emitter layer with a basis of a fourth III-V material having the first type of conductivity with a third N doping level,
said transistor (HBT) further comprising a collector contact on the first layer, at a border of the first mesa structure, a base contact on the base layer, at the border of the second mesa structure, an emitter contact on the emitter layer, said collector, base, and emitter contacts being with a basis of an electrically conductive material, suitable for a metallurgy of the metal levels of a complementary metal-oxide-semiconductor (CMOS) transistor-based integrated circuit, p1 said transistor (HBT) further comprising an encapsulation layer a basis of a dielectric encapsulation material, said encapsulation layer covering the first layer, the first and second mesa structures and the collector, base, and emitter contacts, said encapsulation layer being with a basis of a dielectric material, suitable for an insulation of the metal levels of the CMOS transistor-based integrated circuit, and
wherein the base contact has a central portion and a peripheral portion around the central portion, such that the peripheral portion has a thickness less than that of the central portion and which decreases by moving away from the central portion, so as to decrease a parasitic capacity between the base contact and the emitter contact.

2 more elements

Dependencies are inferred from the claim text.