High-Efficiency Embedded Active Component for Enhanced Channel Loss Compensation

An apparatus, comprising:

• a first integrated circuit (IC) device;
• a second integrated circuit (IC) device;
• and
• an interposer comprising:
• a first plurality of conductive channel segments communicatively coupled to the first IC device;
• a second plurality of conductive channel segments;
• and
• a plurality of bi-directional embedded buffers, wherein each of the plurality of bi-directional embedded buffers is communicatively coupled between a respective one of the first plurality of conductive channel segments and a respective one of the second plurality of conductive channel segments.

An apparatus, comprising:

• a High Bandwidth Memory (HBM) device comprising a first plurality of input/output (I/O) pins;
• a System-on-Chip (SoC) device comprising a second plurality of I/O pins;
• an interposer, wherein each of the HBM device and the SoC device are mounted on and electrically coupled to the interposer;
• a plurality of conductive channels formed in a first layer of the interposer and configured to transmit data between the first plurality of I/O pins and the second plurality of I/O pins;
• and
• a plurality of bi-directional embedded buffers formed in a second layer of the interposer, wherein each of the plurality of bi-directional embedded buffers is electrically coupled to a respective one of the plurality of conductive channels and is configured to reduce losses through the respective one of the plurality of conductive channels.