3D Stackable Memory and Methods of Manufacture

A memory circuit comprising:

• a transistor having a gate, a first source/drain terminal, and a second source/drain terminal;
• a first resistor coupled to the first source/drain terminal;
• a second resistor coupled to the second source/drain terminal;
• a first diode coupled between the first resistor and a first bit line;
• and
• a second diode coupled between the second resistor and a second bit line, the first diode and the second diode being oriented such that a reference voltage applied to the first bit line and a write voltage applied to the second bit line forward-biases the second diode while reverse-biasing the first diode.

A memory device comprising:

• a transistor comprising a channel layer, a gate surrounding a channel region of the channel layer, a first metal line on a first side of the channel region, and a second metal line on a second side of the channel region;
• a first resistive memory film extending from the first metal line on a side of the first metal line opposite the channel region;
• a first electrode coupled to the first resistive memory film;
• a second resistive memory film extending from the second metal line on a side of the second metal line opposite the channel region;
• a second electrode coupled to the second resistive memory film;
• a first diode electrically coupled to the first electrode;
• and
• a second diode electrically coupled to the second electrode.