Method of manufacturing three-dimensional ferroelectric memory devices

A method of manufacturing a three-dimensional ferroelectric memory device, the method comprising:

• forming a conductive pattern and a gate insulation pattern on a substrate, the conductive pattern and the gate insulation pattern being stacked in a horizontal direction substantially parallel to an upper surface of the substrate;
• forming a first source/drain pattern on the substrate adjacent to the gate insulation pattern;
• forming a first channel on an upper surface of the first source/drain pattern and an inner sidewall of the gate insulation pattern, the first channel having a cup shape extending in a vertical direction substantially perpendicular to the upper surface of the substrate;
• forming a filling pattern on the first channel;
• forming a second channel on the first channel and the filling pattern;
• forming a second source/drain pattern on the second channel;
• forming a ferroelectric pattern on a portion of an outer sidewall of the conductive pattern;
• and
• forming a gate electrode on the ferroelectric pattern.

A method of manufacturing a three-dimensional ferroelectric memory device, the method comprising:

• forming a bit line on a substrate, the bit line extending in a first direction substantially parallel to an upper surface of the substrate;
• forming a first source/drain pattern extending in the first direction on the bit line;
• forming a conductive pattern and a gate insulation pattern on the first source/drain pattern, the conductive pattern and the gate insulation pattern being stacked in a horizontal direction substantially parallel to the upper surface of the substrate;
• forming a channel on an upper surface of the first source/drain pattern and an inner sidewall of the gate insulation pattern, the channel extending in a second direction substantially perpendicular to the upper surface of the substrate;
• forming a second source/drain pattern at an upper portion of the channel;
• forming a ferroelectric pattern on a portion of an outer sidewall of the conductive pattern;
• and
• forming a gate electrode on the ferroelectric pattern.