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US 2026/0304778 A1Published application
Ferroelectric memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJeonil Lee, Sam Park
Life of this patent
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Abstract
In a ferroelectric memory device having a vertical channel layer, a 2D material layer, and a ferroelectric layer, the 2D material layer includes an insulating material so that the 2D material layer acts as a gate dielectric layer. The ferroelectric memory device has the 2D material layer between the vertical channel layer and the ferroelectric layer as a gate dielectric layer so as to lessen surface defects of the vertical channel layer, thereby improving durability and reliability.
Claims20
A ferroelectric memory device comprising:
- a source line extending in a first horizontal direction;
- a plurality of vertical channel layers extending in a vertical direction on the source line;
- a two-dimensional (2D) material layer having a plurality of first vertical portions surrounding outer walls of the plurality of vertical channel layers and a first horizontal portion connecting upper portions of the plurality of first vertical portions to one another while extending in the first horizontal direction;
- a ferroelectric layer having a plurality of second vertical portions surrounding outer walls of the plurality of first vertical portions and a second horizontal portion connecting upper portions of the plurality of second vertical portions to one another while extending in the first horizontal direction;
- a plurality of word lines coming into contact with outer walls of the plurality of second vertical portions of the ferroelectric layer, being spaced apart from one another in the first horizontal direction, and extending in a second horizontal direction that crosses the first horizontal direction;
- and
- a bit line coming into contact with the plurality of vertical channel layers and the first horizontal portion of the 2D material layer, and extending in the first horizontal direction.
4 more elements
A ferroelectric memory device comprising:
- a source line extending in a first horizontal direction;
- a plurality of vertical channel layers extending in a vertical direction on the source line;
- a plurality of two-dimensional (2D) material layers extending in a vertical direction while surrounding outer walls of the plurality of vertical channel layers;
- a ferroelectric layer including a plurality of vertical portions surrounding outer walls of the plurality of 2D material layers and a horizontal portion extending in the first horizontal direction while connecting upper portions of the plurality of vertical portions;
- a plurality of word lines coming into contact with an outer wall of the ferroelectric layer, being spaced apart from one another in the first horizontal direction, and extending in a second horizontal direction that crosses the first horizontal direction;
- and
- a bit line extending in the first horizontal direction while coming into contact with the plurality of vertical channel layers, the plurality of 2D material layers, and the horizontal portion of the ferroelectric layer,
- wherein the plurality of word lines have gate-all-around (GAA) structures surrounding the plurality of vertical channel layers corresponding thereto.
5 more elements
A ferroelectric memory device comprising:
- a source line extending in a first horizontal direction;
- a vertical channel layer including an oxide semiconductor material and having an inner wall and an outer wall, on the source line;
- a two-dimensional (2D) material layer conformally arranged on the inner wall of the vertical channel layer;
- a ferroelectric layer conformally arranged on an inner wall of the 2D material layer;
- a pair of word lines that are arranged on both side walls of the ferroelectric layer and extend in a second horizontal direction crossing the first horizontal direction;
- and
- a bit line coming into contact with the vertical channel layer and extending in the first horizontal direction.
4 more elements
Dependencies are inferred from the claim text.