Memory devices having pillar interior select
AssigneeMicron Technology, Inc.
InventorsDarwin A. Clampitt, Collin Howder, Vladimir Samara
Life of this patent
Estimating the term…
Abstract
A variety of applications can include a memory device having an array of pillars with memory cells arranged in tiers along the pillars. Drain-side select gate (SGD) transistors can be structured substantially in the pillar at a level above the memory cells. The gate of the SGD transistor can be formed in the center of the respective pillar. In various arrangements, the gate of a SGD transistor interior to a pillar of memory cells can be arranged to operate with dual channels of the pillar. Additional devices, systems, and methods are discussed.
Claims20
A memory device comprising:
- a vertical string of memory cells, with each memory cell of the vertical string arranged in a tier along a pillar, with a cell channel of each memory cell being a portion of a vertical channel structure to the pillar, the vertical channel structure to the pillar vertically adjacent and contacting dielectric fill of the pillar;
- and
- a drain-side select gate (SGD) transistor structured substantially in the pillar at a level above the memory cells, the SGD transistor having a gate directly above the dielectric fill of the pillar and having a channel structure extending from the vertical channel structure of the pillar.
A memory device comprising:
- rows of pillars, arrangement of each pillar including:
- a first vertical string of memory cells arranged in tiers along the pillar, with a cell channel of each memory cell of the first vertical string being a portion of a first vertical channel structure to the pillar, the first vertical channel structure to the pillar vertically adjacent and contacting dielectric fill of the pillar;
- a second vertical string of memory cells arranged in tiers along the pillar, with a cell channel of each memory cell of the second vertical string being a portion of a second vertical channel structure to the pillar, the second vertical channel structure to the pillar vertically adjacent and contacting the dielectric fill of the pillar, the second vertical channel structure separated from the first vertical channel structure by the dielectric fill;
- and
- a drain-side select gate (SGD) transistor structured substantially in the pillar at a level above the memory cells of the first and second strings, the SGD transistor having a gate directly above the dielectric fill of the pillar, and a first channel structure extending from the first vertical channel structure of the pillar, and a second channel structure extending from the second vertical channel structure of the pillar.
A method of forming a memory device, the method including:
- forming a vertical string of memory cells, with each memory cell of the vertical string arranged in a tier along a pillar, with a cell channel of each memory cell being a portion of a vertical channel structure to the pillar, the vertical channel structure to the pillar vertically adjacent and contacting dielectric fill of the pillar;
- and
- forming a drain-side select gate (SGD) transistor structured substantially in the pillar at a level above the memory cells, the SGD transistor having a gate directly above the dielectric fill of the pillar and having a channel structure extending from the vertical channel structure of the pillar.
Dependencies are inferred from the claim text.