Semiconductor device, memory and manufacturing method therefor, and electronic device

A memory, comprising:

• a substrate;
• a memory cell array, comprising a plurality of layers of memory cells stacked in a first direction, wherein memory cells located in a same layer among the plurality of layers of memory cells are arranged in columns in a second direction and arranged in rows in a third direction, the first direction is perpendicular to a surface of the substrate, the second direction is parallel to the surface of the substrate, and the third direction is parallel to the surface of the substrate and intersects with the second direction;
• each of the memory cells comprises transistors, the transistor comprises a semiconductor layer, the semiconductor layer is provided with two opposite main surfaces, the two opposite main surfaces are a first side and a second side of the semiconductor layer respectively, and the semiconductor layer comprises, on the first side, a source contact region and a drain contact region spaced apart from each other, and a channel region between the source contact region and the drain contact region;
• a plurality of bit lines (BLs), wherein a same BL extending along the first direction is shared by all layers of memory cells located at a same position of the memory cell array, and each of the plurality of BLs is arranged on the first side of a corresponding one of the semiconductor layers and is connected to the drain contact region of the corresponding one of the semiconductor layers;
• and
• a plurality of word lines (WLs), wherein a same WL extending along the second direction is shared by memory cells located in a same column among the memory cells located in the same layer, and each of the plurality of WLs is arranged on the second side of a respective one of the semiconductor layers.

A method for preparing a memory, comprising:

• providing a substrate, and forming multilayer stacked units on the substrate, wherein each of the multilayer stacked units comprises sacrificial layers and interlayer dielectric layers sequentially and alternately stacked along a first direction perpendicular to a surface of the substrate;
• back etching a sidewall of each sacrificial layer in a second direction, to form a first accommodation groove, and sequentially forming an initial semiconductor layer, a gate dielectric layer and a word line (WL) on an inner wall of the first accommodation groove, wherein the second direction is parallel to the surface of the substrate;
• etching the sacrificial layers, the interlayer dielectric layers and the initial semiconductor layers along the first direction, to separate the initial semiconductor layer into a plurality of semiconductor layers arranged at intervals in the second direction, wherein each of the semiconductor layers is provided with two opposite main surfaces, the two opposite main surfaces are a first side away from the WL and a second side facing towards the WL respectively, and each of the semiconductor layers comprises, on the first side, a source contact region and a drain contact region spaced apart from each other, and a channel region located the source contact region and the drain contact region;
• forming, in a first area of the multilayer stacked unit, a bit line (BL) hole which penetrates the multilayer stacked unit in the first direction and exposes the drain contact region of each corresponding layer;
• forming a BL in the BL hole;
• forming, in a second area of each of the multilayer stacked units, an etching groove which penetrates the multilayer stacked unit in the first direction and extends along the second direction, wherein each second area has a spacing from the first area in a third direction, and the second direction and the third direction are parallel to the surface of the substrate and intersect with each other;
• etching the sacrificial layer, to form a second accommodation groove and expose the source contact region of a corresponding layer, wherein the second accommodation groove has a spacing from the BL hole in each of the second direction and the third direction;
• and
• forming a capacitor in the second accommodation groove.