Semiconductor devices and fabricating methods thereof

A semiconductor device, comprising:

• an insulating wall extending along a first direction and a second direction perpendicular to the first direction, the insulating wall having a first side and a second side opposite each other in a third direction perpendicular to the first direction and second direction;
• a first gate electrode layer and a second gate electrode layer extending along the first direction and coupled to the first side and the second side of the insulating wall, respectively;
• and
• a first semiconductor layer and a second semiconductor layer extending along the first direction and coupled to the first gate electrode layer and the second gate electrode layer respectively;
• wherein
• a first distance between a first end of the first semiconductor layer and a first end of the second semiconductor layer is smaller than a second distance between a second end of the first semiconductor layer and a second end of the second semiconductor layer;
• the first end of the first semiconductor layer is coupled to a first bit line;
• the first end of the second semiconductor layer is coupled to the first bit line;
• the second end of the first semiconductor layer is coupled to a first storage unit;
• and
• the second end of the second semiconductor layer is coupled to a second storage unit.

A method of fabricating a semiconductor device, comprising:

• forming an insulating wall extending along a first direction and a second direction perpendicular to the first direction, the insulating wall having a first side and a second side opposite to each other in a third direction perpendicular to the first direction and second direction;
• forming a first gate electrode layer and a second gate electrode layer extending along the first direction and coupled to the first side and the second side of the insulating wall respectively;
• and
• forming a first semiconductor layer and a second semiconductor layer extending along the first direction and coupled to the first gate electrode layer and the second gate electrode layer respectively;
• wherein
• the first gate electrode layer and the second gate electrode layer are disposed between the first semiconductor layer and the second semiconductor layer in the third direction.