Semiconductor structure and method of manufacturing the same

A method for manufacturing a semiconductor structure, comprising:

• forming word lines in a second dielectric layer on a first dielectric layer including memory elements, wherein the word lines are arranged in parallel along a first direction;
• forming a third dielectric layer over the second dielectric layer;
• partially etching the third dielectric layer to form a plurality of first trenches;
• filling the plurality of first trenches with first conductive materials and first hydrogen absorption materials to form a plurality of source regions and a plurality of first barrier structures, wherein the plurality of source regions electrically connects the memory elements;
• applying a first sacrificial layer onto the third dielectric layer and the plurality of source regions;
• patterning the first sacrificial layer to form patterned first sacrificial regions defining locations for a plurality of channel regions, which correspond locations of the source regions;
• applying dielectric materials onto the patterned first sacrificial regions and the third dielectric layer uncovered by the patterned first sacrificial regions;
• patterning the dielectric materials to remove portions of the dielectric materials to form gaps surrounding the patterned first sacrificial regions, wherein remaining portions of the dielectric materials form a fourth dielectric layer on the third dielectric layer;
• filling the gaps with conductive materials to form gate electrodes;
• applying first insulating materials onto the fourth dielectric layer, the gate electrodes and the patterned first sacrificial regions;
• patterning the first insulating materials to form an insulating layer with a plurality of first recesses to partially expose a top of each of the patterned first sacrificial regions;
• removing the patterned first sacrificial regions to form a plurality of second recesses above the source regions;
• conformally forming gate dielectric layers along sidewalls of the second recesses and sidewalls of the first recesses;
• conformally forming channel layers on the third dielectric layer and along the gate dielectric layers;
• filling each of the second recesses and each of the first recesses with a second insulating materials so as to form a central isolation structure with the channel layer as a bottom and a sidewall;
• forming a fifth dielectric layer over the fourth dielectric layer;
• etching the fifth dielectric layer to form a plurality of second trenches;
• and
• filling the plurality of second trenches with second conductive materials and second hydrogen absorption materials to form a plurality of drain regions and a plurality of second barrier structures on the channel regions.

A semiconductor structure, comprising:

• a first dielectric layer comprising a plurality of memory elements;
• a second dielectric layer stacking over the first dielectric layer along a first direction and comprising a plurality of first conductive lines arranged in parallel along a second direction, perpendicular to the first direction;
• a third dielectric layer stacking over the second dielectric layer along the first direction and comprising:
• a plurality of first conductive regions electrically connecting the memory elements;
• and
• a plurality of first barrier structures formed on bottoms or tops of the plurality of first conductive regions;
• a fourth dielectric layer stacking over third dielectric layer and comprising channel regions, each of the channel regions comprising:
• a central portion comprising a central isolation structure and a channel layer, wherein the channel layer electrically connects a corresponding one of the first conductive regions;
• a gate dielectric layer formed around the channel layer so that the channel layer is sandwiched by the gate dielectric layer and the central isolation structure;
• and
• a gate electrode formed along the gate dielectric layers and electrically connecting the plurality of first conductive lines;
• a fifth dielectric layer stacking over the fourth dielectric layer along the first direction and comprising:
• a plurality of second conductive regions electrically connecting the channel layer;
• and
• a plurality of second barrier structures formed on the central portions of the channel regions,
• wherein the gate electrode is formed between the third dielectric layer and the fourth dielectric layer, and
• wherein the plurality of first barrier structures and the plurality of second barrier structures comprise hydrogen absorption materials.