Wiring board and method for producing same

A method for manufacturing a wiring board, comprising:

• forming a first insulating layer comprising a first upper surface;
• forming a wide pattern on the first upper surface, the wide pattern comprising a first underlying metal layer and a first electrolytic plating layer located on the first underlying metal layer, the wide pattern having a width of not less than 150 μm;
• forming a second insulating layer covering the first upper surface and the wide pattern, the second insulating layer comprising a second upper surface;
• forming a first groove and a second groove recessed from the second upper surface toward the first insulating layer side, the first groove comprising a first inner surface in contact with a side surface of the wide pattern, the second groove comprising a second inner surface spaced apart from the wide pattern;
• forming a second underlying metal layer covering the first inner surface, a third underlying metal layer covering the second inner surface, a fourth underlying metal layer covering the second upper surface and being continuous with the second underlying metal layer and the third underlying metal layer, a second electrolytic plating layer located on the second underlying metal layer, the second electrolytic plating layer having a thickness to fill the first groove, a third electrolytic plating layer located on the third underlying metal layer, the third electrolytic plating layer having a thickness to fill the second groove, and a fourth electrolytic plating layer located on the fourth underlying metal layer and continuous with the second electrolytic plating layer and the third electrolytic plating layer;
• and
• forming a first wiring conductor located from the first groove to the first upper surface and comprising the wide pattern, a second wiring conductor located in the second groove and comprising thea narrow pattern having a width of not more than 15 μm, by at least removing the fourth underlying metal layer and the fourth electrolytic plating layer located on the second upper surface.