Simplified log-likelihood ratio demapper
AssigneeSilicon Laboratories Inc.
InventorsXushuai Qu, Guner Arslan, Wentao Li
Life of this patent
Estimating the term…
Loading patent…
AssigneeSilicon Laboratories Inc.
InventorsXushuai Qu, Guner Arslan, Wentao Li
Estimating the term…
A technique for reducing complexity and power consumption of generation of Log-Likelihood Ratio (LLR) values in a Phase-Shift Keying digital communications system includes rotating a received symbol and providing the rotated symbols to a simplified LLR demapper that generates an LLR value for each coded bit of the phase-rotated received symbol based on the phase-rotated received symbol and a set of predetermined scalar values. An embodiment of the simplified LLR demapper includes scaling circuits that multiply the signal components and scalar values using shift and add operations. A select circuit selects outputs of the scaling circuits as in-phase and quadrature components of the LLR values for each coded bit of the received symbol based on a control code generated based on the rotated symbol. The simplified LLR demapper combines the outputs of the select circuits to generate the LLR values for each coded bit of the received symbol.
A receiver of a digital communications system using shift keying digital modulation, the receiver comprising:
A method for calculating log-likelihood ratio (LLR) values in a digital communications system using shift keying digital modulation, the method comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.