Systems and Methods for Communicating using Time Shift Signaling

A receiver capable of receiving data transmitted via time shift (TS) signaling, comprising:

• interface circuitry capable of transmitting data to a serializer-deserializer (SERDES) circuit;
• a TS decoder capable of receiving an analog signal via a communication channel and outputting a series of recovered bits to the interface circuitry, where the TS decoder comprises:
• N sample and hold circuits that are each delayed from each other by a time period T/N;
• N analog-to-digital converters (ADCs), where each of the N sample and hold circuits is capable of providing an output to a corresponding ADC;
• N receiver equalizers, where each of the N ADCs is capable of providing an output to a corresponding receiver equalizer;
• a TS Inter-Symbol Interference (ISI) canceller and a Decision Feedback Equalizer (DFE) equalizer, where:
• each of the N receiver equalizers provides an output to the TS ISI canceller and DFE equalizer;
• and
• the TS ISI canceller and DFE equalizer utilizes samples at intervals of N/T from each of the outputs provided by the N receiver equalizers to generate output symbols;
• and
• a decoder, where:
• the TS ISI canceller and DFE equalizer is capable of providing the generated output symbols to the decoder;
• and
• the decoder generates the series of recovered bits based upon the provided output symbols.

An integrated circuit capable of communicating via time shift (TS) signaling comprising:

• a serializer-deserializer (SERDES) circuit;
• circuits coupled to the SERDES circuit, where the SERDES is capable of transmitting and receiving parallel data to and from the circuits coupled to the SERDES circuit;
• a linear transceiver, where the linear transceiver is capable of transmitting and receiving high-speed serial data to and from the SERDES circuit;
• wherein the linear transceiver comprises:
• interface circuitry capable of transmitting and receiving data to and from the serializer-deserializer (SERDES) circuit;
• a TS encoder capable of receiving a series of N bits (B0, B1, . . . , BN−1) from the interface circuitry, where the TS encoder comprises:
• a plurality of separate encoder and transmit equalizer, where:
• each bit is provided to one of the plurality of separate encoder and transmit equalizers to produce N symbols based upon the series of N bits;
• and
• the plurality of separate encoder and transmit equalizers include at least:
• a first encoder and transmit equalizer capable of producing a digital representation of a first symbol (S0) having a time period T based upon a first bit (B0) of the series of N bits;
• a second encoder and transmit equalizer capable of producing a digital representation of a second symbol (S1) having a time period T based upon a second bit (B1) of the series of N bits, where the second symbol is time delayed by a period of T/N relative to the first symbol;
• and a third encoder and transmit equalizer capable of producing a digital representation of a third symbol (S2) having a time period T based upon a third bit (B2) of the series of N bits, where the third symbol is time delayed by a period of T/N relative to the second symbol;
• a summing circuit capable of summing each of the N symbols output by the separate encoder and transmit equalizers at each T/N time interval during the symbol time period T of the first symbol (S0) to produce a series of summed values;
• a digital-to-analog converter capable of producing an analog waveform based upon the series of summed values;
• and
• a driver circuit capable of generating a signal on a first communication channel based upon the analog waveform;
• a TS decoder capable of receiving an analog signal via a second communication channel and outputting a series of recovered bits to the interface circuitry, where the TS decoder comprises:
• N sample and hold circuits that are each delayed from each other by a time period T/N;
• N analog-to-digital converters (ADCs), where each of the N sample and hold circuits is capable of providing an output to a corresponding ADC;
• N receiver equalizers, where each of the N ADCs is capable of providing an output to a corresponding receiver equalizer;
• a TS Inter-Symbol Interference (ISI) canceller and a Decision Feedback Equalizer (DFE) equalizer, where:
• each of the N receiver equalizers provides an output to the TS ISI canceller and DFE equalizer;
• and
• the TS ISI canceller and DFE equalizer utilizes samples at intervals of N/T from each of the outputs provided by the N receiver equalizers to generate output symbols;
• and
• a decoder, where:
• the TS ISI canceller and DFE equalizer is capable of providing the generated output symbols to the decoder;
• and
• the decoder generates the series of recovered bits based upon the provided output symbols.