Mimo equalizer circuit, communication unit and method for successive interference cancellation

A multiple-input multiple-output, MIMO, equalizer circuit comprising:

• a controller;
• an inverse square root matrix circuit operably coupled to the controller and having a first input operable to receive a covariance matrix, RI, and configured to perform an inverse square root operation to the covariance matrix, RI, and output an inverted square root covariance matrix, RI−1/2, to a first output;
• an interference rejection combining, IRC-preprocessing circuit operably coupled to the controller and the inverse square root matrix circuit and comprises a channel estimate matrix, H, input and a received signal vector, y, input wherein the IRC-preprocessing circuit is configured to:
• multiply the inverted square root covariance matrix, RI−1/2, and a channel estimate matrix, H, that generates a preprocessed channel estimate, H2, matrix provided to a second output;
• and
• multiply the inverted square root covariance matrix, RI−1/2, and the received signal vector, y, that generates a preprocessed received signal, y1, vector provided to a third output;
• a matrix extension circuit operably coupled to the controller and the second output and third output of the IRC-preprocessing circuit, wherein the matrix extension circuit is configured to:
• extend the preprocessed channel estimate, H2, matrix that produces a preprocessed channel estimate, H3, matrix provided to a fourth output;
• and
• extend the preprocessed received signal, y1, vector that produces an extended preprocessed received signal, y2, vector provided to a fifth output;
• and
• a successive interference cancellation, SIC, detection circuit operably coupled to the controller and the fourth output and fifth output of the matrix extension circuit, wherein the SIC detection circuit is configured to use the extended preprocessed channel estimate, H3, matrix to perform successive interference cancellation to the extended preprocessed received signal, y2, vector that produces an equalized signal vector, x;
• wherein the inverse square root matrix circuit comprises:
• a Schur decomposition circuit operably coupled to the first input and configured to convert the covariance matrix, R1, into an orthogonal eigenvectors matrix, U, and a real-valued diagonal matrix, D;
• an inverse square root circuit operably coupled to the Schur decomposition circuit and configured to perform an inverse square root operation that converts the real-valued diagonal matrix, D, into an inverted square root real-valued diagonal matrix, D−1/2;
• and
• a matrix manipulation circuit operably coupled to the Schur decomposition circuit and the inverse square root circuit and configured to generate a B1 matrix from the orthogonal eigenvectors matrix, U, and the inverted square root real-valued diagonal matrix, D−1/2, to the first output.

A communication unit comprising a multiple-input multiple-output, MIMO, equalizer circuit comprising:

• a controller;
• an inverse square root matrix circuit operably coupled to the controller and having a first input operable to receive a covariance matrix, RI, and configured to perform an inverse square root operation to the covariance matrix, RI, and output an inverted square root covariance matrix, RI−1/2, to a first output;
• an interference rejection combining, IRC-preprocessing circuit operably coupled to the controller and the inverse square root matrix circuit and comprises a channel estimate matrix, H, input and a received signal vector, y, input wherein the IRC-preprocessing circuit is configured to:
• multiply the inverted square root covariance matrix, RI−1/2, and a channel estimate matrix, H, that generates a preprocessed channel estimate, H2, matrix provided to a second output;
• and
• multiply the inverted square root covariance matrix, RI−1/2, and the received signal vector, y, that generates a preprocessed received signal, y1, vector provided to a third output;
• a matrix extension circuit operably coupled to the controller and the second output and third output of the IRC-preprocessing circuit, wherein the matrix extension circuit is configured to:
• extend the preprocessed channel estimate, H2, matrix that produces a preprocessed channel estimate, H3, matrix provided to a fourth output;
• and
• extend the preprocessed received signal, y1, vector that produces an extended preprocessed received signal, y2, vector provided to a fifth output;
• and
• a successive interference cancellation, SIC, detection circuit operably coupled to the controller and the fourth output and fifth output of the matrix extension circuit, wherein the SIC detection circuit is configured to use the extended preprocessed channel estimate H3 matrix to perform successive interference cancellation to the extended preprocessed received signal, y2, vector that produces an equalized signal vector, x;
• wherein the inverse square root matrix circuit comprises:
• a Schur decomposition circuit operably coupled to the first input and configured to convert the covariance matrix, RI, into an orthogonal eigenvectors matrix, U, and a real-valued diagonal matrix, D;
• an inverse square root circuit operably coupled to the Schur decomposition circuit and configured to perform an inverse square root operation that converts the real-valued diagonal matrix, D, into an inverted square root real-valued diagonal matrix, D−1/2;
• and
• a matrix manipulation circuit operably coupled to the Schur decomposition circuit and the inverse square root circuit and configured to generate a B1 matrix from the orthogonal eigenvectors matrix, U, and the inverted square root real-valued diagonal matrix D−1/2 to the first output.

A method of performing multiple-input multiple-output, MIMO, equalization comprising:

• at an inverse square root matrix circuit:
• receiving a covariance matrix, RI;
• converting, by a Schur decomposition circuit, the covariance matrix, RI, into an orthogonal eigenvectors matrix, U, and a real-valued diagonal matrix, D;
• performing an inverse square root operation that converts the real-valued diagonal matrix, D, into an inverted square root real-valued diagonal matrix D−1/2, by an inverse square root circuit operably coupled to the Schur decomposition circuit;
• generating a B1 matrix from an orthogonal eigenvectors matrix, U, and the inverted square root real-valued diagonal matrix, D−1/2, by a matrix manipulation circuit operably coupled to the Schur decomposition circuit and the inverse square root circuit;
• and
• outputting an inverted square root covariance matrix, RI−1/2;
• receiving by an interference rejection combining, IRC-preprocessing circuit the inverted square root covariance matrix, RI−1/2, a channel estimate matrix H, and a received signal vector, y;
• multiplying the inverted square root covariance matrix, RI−1/2, and the channel estimate matrix, H, and generating a preprocessed channel estimate, H2, matrix;
• multiplying the inverted square root covariance matrix, RI−1/2, and the received signal vector y and generating a preprocessed received signal, y1, vector;
• extending the preprocessed channel estimate, H2, matrix by a matrix extension circuit and producing a preprocessed channel estimate, H3, matrix;
• extending the preprocessed received signal, y1, vector and producing an extended preprocessed received signal, y2, vector;
• and
• receiving by a successive interference cancellation, SIC, detection circuit the extended preprocessed channel estimate, H3, matrix, and using the extended preprocessed channel estimate, H3, matrix to perform successive interference cancellation to the extended preprocessed received signal, y2, vector and outputting an equalized signal vector x.