Methods and apparatus for echo cancellation in transceivers

An apparatus comprising:

• combination circuitry having:
• a first resistor having a first terminal and a second terminal;
• a second resistor having a first terminal and a second terminal, the second terminal of the second resistor coupled to the second terminal of the first resistor;
• a third resistor having a first terminal and a second terminal;
• a fourth resistor having a first terminal and a second terminal, the second terminal of the fourth resistor coupled to the second terminal of the third resistor;
• a fifth resistor having a first terminal and a second terminal, the first terminal of the fifth resistor coupled to the second terminal of the first resistor and the second terminal of the second resistor;
• and
• a sixth resistor having a first terminal and a second terminal, the first terminal of the sixth resistor coupled to the second terminal of the fifth resistor, the second terminal of the sixth resistor coupled to the second terminal of the third resistor and the second terminal of the fourth resistor;
• a comparator having a first input, a reference terminal, and an output, the first input of the comparator coupled to the second terminal of the fifth resistor and to the first terminal of the sixth resistor;
• a first current source coupled to the output of the comparator, to the second terminal of the first resistor, to the second terminal of the second resistor, and to the first terminal of the fifth resistor;
• and
• a second current source coupled to the output of the comparator, to the second terminal of the third resistor, to the second terminal of the fourth resistor, and to the second terminal of the sixth resistor.

A system comprising:

• a communication channel having an output;
• replica transmitter circuitry having an output;
• combination circuitry including:
• voltage to current converter circuitry including:
• a first resistor having a first terminal and a second terminal, the first terminal coupled to the output of the communication channel;
• a second resistor having a first terminal and a second terminal, the first terminal of the second resistor coupled to the output of the replica transmitter circuitry, the second terminal of the second resistor coupled to the second terminal of the first resistor;
• a third resistor having a first terminal and a second terminal, the first terminal coupled to the output of the communication channel;
• and
• a fourth resistor having a first terminal and a second terminal, the first terminal of the fourth resistor coupled to the output of the replica transmitter circuitry, the second terminal of the fourth resistor coupled to the second terminal of the third resistor;
• virtual ground circuitry including:
• a first transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the first transistor coupled to the second terminals of the first resistor and second resistor;
• a second transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the second transistor coupled to the first terminal of the first transistor;
• a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal coupled to the control terminal of the first transistor, the second terminal of the third transistor coupled to the second terminals of the third resistor and the fourth resistor, the, and the control terminal of the third transistor coupled to the first terminal of the first transistor and to the second terminal of the second transistor;
• and
• a fourth transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the fourth transistor coupled to the first terminal of the third transistor and to the control terminal of the first transistor, the control terminal of the fourth transistor coupled to control terminal of the second transistor;
• and
• receiver circuitry having an input, the input of the receiver circuitry coupled to the first terminal of the second transistor and to the first terminal of the fourth transistor.