Methods and apparatus to compensate for non-linearity in interleaved digital-to-analog converters

A digital-to-analog converter (DAC) comprising:

• control circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal;
• a first switch having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the control circuitry;
• a first DAC core having a positive output, a negative output, and an input coupled to the second terminal of the first switch;
• a second switch having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the second terminal of the control circuitry, the first terminal coupled to the first terminal of the first switch;
• a second DAC core having a positive output, a negative output, and an input coupled to the second terminal of the second switch;
• a multiplexer having a positive output, a negative output, a first positive input coupled to the positive output of the first DAC core, a first negative input coupled to the negative output of the first DAC core, a second positive input coupled to the positive output of the second DAC core, a second negative input coupled to the negative output of the second DAC core, a first control terminal coupled to the third terminal of the control circuitry, and a second control terminal coupled to the fourth terminal of the control circuitry;
• an output termination network having a positive input coupled to the positive output of the multiplexer and a negative input coupled to the negative output of the multiplexer;
• and
• a compensation network having a positive input coupled to the positive output of the multiplexer, a negative input coupled to the negative output of the multiplexer, a positive supply terminal coupled to the negative output of the multiplexer, and a negative supply terminal coupled to the positive output of the multiplexer.

An apparatus comprising:

• a multiplexer having a positive output and a negative output;
• a first capacitor having a first terminal and a second terminal coupled to the positive output of the multiplexer;
• a first lead compensator (LC) circuit having an output and an input coupled to the first terminal of the first capacitor;
• a second capacitor having a first terminal and a second terminal coupled to the positive output of the multiplexer;
• a second LC circuit having an output and an input coupled to the first terminal of the second capacitor;
• a first cancellation circuit having a first input coupled to the output of the first LC circuit, a second input coupled to the output of the second LC circuit, a first voltage terminal coupled to the negative output of the multiplexer, and a second voltage terminal coupled to a ground terminal;
• a third capacitor having a first terminal and a second terminal coupled to the negative output of the multiplexer;
• a third LC circuit having an output and an input coupled to the first terminal of the third capacitor;
• a fourth capacitor having a first terminal and a second terminal coupled to the negative output of the multiplexer;
• a fourth LC circuit having an output and an input coupled to the first terminal of the fourth capacitor;
• and
• a second cancellation circuit having a first input coupled to the output of the third LC circuit, a second input coupled to the output of the fourth LC circuit, a first voltage terminal coupled to the positive output of the multiplexer, and a second voltage terminal coupled to the ground terminal.