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AssigneeSamsung Electronics Co., Ltd.
InventorsHyungjun KIM, Jaewoo Park, Myoungbo Kwak, Seungyeob Baek, Jinook Jung
Estimating the term…
A phase locked loop is provided. The phase locked loop includes: a digitally controlled oscillator configured to generate an output clock according to a frequency control signal; a frequency divider circuit configured to generate a feedback clock by frequency dividing the output clock based on a first divide ratio value; a phase detection circuit configured to generate a phase difference signal according to a phase difference between the feedback clock and an externally provided reference clock; a loop filter circuit configured to generate a frequency control raw signal based on the phase difference signal; and a peaking suppression circuit configured to generate the frequency control signal by limiting a fluctuation range of the frequency control raw signal.
A phase locked loop, comprising:
An operation method of a phase locked loop including a digitally controlled oscillator generating an output clock according to a frequency control signal, the operation method comprising:
A phase locked loop, comprising:
Dependencies are inferred from the claim text.