Phase locked loop circuit to minimize circuit noise

Abstract

The present application relates to a phase locked loop circuit. The phase locked loop circuit according to some embodiments of the present disclosure includes: a control voltage generation unit configured to generate a control voltage by comparing a reference signal with a feedback signal, and control a common mode noise by adjusting a common mode voltage of the control voltage based on a trip point of an inverter circuit; and a voltage controlled oscillator configured to output an output signal in response to the control voltage and feed back the output signal to the feedback signal, wherein the inverter circuit may modulate the noise of the bias charge pump to the common mode noise through a replica path electrically connected to a rear end of the bias charge pump.

Dependencies are inferred from the claim text.