Power-on reset circuit
AssigneeHuahong Integrated Circuit(Chengdu) Corporation
InventorsChen CHEN, Zhili WANG, Yifei QIAN
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Abstract
The present disclosure discloses a power-on reset circuit. A sixth PMOS transistor and a second resistor are added based on an existing power-on reset circuit structure. The sixth PMOS transistor is positioned in a branch of first PMOS transistor-zeroth NMOS transistor, and a second resistor is positioned in a branch of zeroth PMOS transistor-zeroth resistor-first resistor. It may be ensured that a normal function of the power-on reset circuit to detect a voltage of a power supply is not affected, and the branch of first PMOS transistor-zeroth NMOS transistor is turned off after a voltage of a power supply is established to reduce overall power consumption of the power-on reset circuit.
Claims10
A power-on reset circuit, comprising a zeroth PMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a zeroth NMOS transistor, a first NMOS transistor, a zeroth resistor, a first resistor, a second resistor, a first inverter, a second inverter, a third inverter, and a reset capacitor,
- wherein source terminals of the zeroth PMOS transistor, the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected to a power supply voltage;
- the second resistor, the zeroth resistor, and the first resistor are sequentially connected in series between the third node and ground;
- the zeroth PMOS transistor has a drain terminal connected to the third node and a gate terminal connected to a gate terminal of the first PMOS transistor, a gate terminal of the second PMOS transistor, and a series connection point between the second resistor and the zeroth resistor;
- a drain terminal of the first PMOS transistor is connected to a source terminal of the sixth PMOS transistor;
- the sixth PMOS transistor has a drain terminal connected to a first node and a gate terminal connected to the third node;
- the third PMOS transistor has a gate terminal connected to the first node, and a drain terminal connected to a drain terminal of the fourth PMOS transistor and a gate terminal of the zeroth NMOS transistor;
- the fourth PMOS transistor has a source terminal connected to a series connection point between the zeroth resistor and the first resistor, and a gate terminal connected to an output terminal of the first inverter;
- the zeroth NMOS transistor has a source terminal that is connected to the ground and a drain terminal connected to the first node;
- the first inverter and the second inverter are sequentially connected in series between the first node and a second node;
- a drain terminal of the second PMOS transistor is connected to the source terminal of the fifth PMOS transistor;
- the fifth PMOS transistor has a gate terminal connected to the second node and a gate terminal of the first NMOS transistor, and a drain terminal connected to a drain terminal of the first NMOS transistor and an upper plate of the reset capacitor;
- a source terminal of the first NMOS transistor is connected to the ground;
- a lower plate of the reset capacitor is connected to the ground;
- and
- the third inverter has an input terminal connected to the upper plate of the reset capacitor, and an output terminal used for outputting a low-level reset signal.
Dependencies are inferred from the claim text.