Semiconductor device
AssigneeRenesas Electronics Corporation
InventorToshiki KIRYU
Life of this patent
Estimating the term…
Abstract
An internal reset generation circuit asserts a reset request signal when a reset factor is detected. A pulse generation circuit generates a reset-out drive pulse signal, and controls a switch to an ON state/OFF state during an assertion period/negation period of the reset-out drive pulse signal. In more detail, a reset-out period setting register holds a count setting value representing a length of the assertion period of the reset-out drive pulse signal. A counter counts a clock signal starting from assertion of the reset request signal until the count setting value is reached, thereby generating the reset-out drive pulse signal.
Claims6
A semiconductor device comprising:
- an external terminal capable of outputting a reset-out signal to an external device;
- a switch configured to apply a reset voltage to the external terminal during an ON-state period, thereby controlling the reset-out signal to the reset voltage corresponding to an assertion level;
- an internal reset generation circuit configured to assert a reset request signal when a reset factor is detected;
- and
- a pulse generation circuit configured to generate a reset-out drive pulse signal and control the switch to an ON state/OFF state during an assertion period/negation period of the reset-out drive pulse signal,
- wherein the pulse generation circuit includes:
- a clock generation circuit configured to generate a clock signal;
- a reset-out period setting register configured to hold a count setting value representing a length of the assertion period of the reset-out drive pulse signal;
- and
- a counter configured to count the clock signal starting from assertion of the reset request signal until the count setting value is reached, thereby generating the reset-out drive pulse signal.
Dependencies are inferred from the claim text.