Methods and apparatus for reducing leakage currents in cmos

Abstract

Aspects of the present disclosure include methods for reducing leakage current including identifying a commutative circuit of a plurality of circuits, the commutative circuit being configured to receive a first logical input signal via a first terminal and a second logical input signal via a second terminal, identifying a first leakage current associated with a first state of the commutative circuit and a second leakage current associated with a second state of the commutative circuit, the first leakage current being larger than the second leakage current, and switching, at a software level, the first logical input signal and the second logical input signal such that the commutative circuit receives the first logical input signal via the second terminal and the second logical input signal via the first terminal.

Dependencies are inferred from the claim text.