Systems and methods for duty-cycle and phase error detector (dped) with chopping cancellation technique

A circuit, comprising:

• a first multiplexer configured to receive a first clock signal with a 0° phase, a second clock signal with a 90° phase, a third clock signal with a 180° phase, and a fourth clock signal with a 270° phase, and, when in a first mode, select a first plurality of the first to fourth clock signals as a first output and a second output, respectively;
• a second multiplexer configured to receive the first to fourth clock signals, and, when in a second mode, select a second plurality of the first to fourth clock signals;
• a combination of logic gates comprising a first logic gate and a second logic gate, wherein the combination of logic gates is coupled to the second multiplexer and, when in the second mode, configured to receive the second plurality of the first to fourth clock signals, provide a third output through the first logic gate, and provide a fourth output through the second logic gate;
• a first low-pass filter configured to provide a first direct current (DC) voltage based on the first and third outputs;
• and
• a second low-pass filter configured to provide a second DC voltage based on the second and fourth outputs.

A method for operating a circuit, comprising:

• selecting, by a multiplexer of the circuit, during a first mode to detect duty cycles of a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, a first plurality of the first to fourth clock signals as a first output and a second output, respectively;
• filtering, by a first low-pass filter and a second low-pass filter of the circuit, the first output and the second output to provide a first direct current (DC) voltage and a second DC voltage, respectively;
• XOR'ing, by a first logic gate of the circuit, during a second mode to detect phases of the first to fourth clock signals, a second plurality of the first to fourth clock signals as a third output;
• XNOR'ing, by a second logic gate of the circuit, during the second mode, a third plurality of the first to fourth clock signals as a fourth output;
• and
• filtering, by the first low-pass filter and the second low-pass filter of the circuit, the third output and the fourth output to provide the first DC voltage and the second DC voltage, respectively.