Duty cycle correction circuit

A duty cycle correction circuit comprising:

• a duty adjustment circuit configured to adjust phases of a plurality of external clock signals according to a plurality of codes to generate a plurality of duty correction clock signals;
• a duty detection circuit configured to generate a plurality of duty detection signals according to the plurality of duty correction clock signals;
• a code adjustment clock generation circuit configured to generate a plurality of code adjustment clock signals for varying a second code among the plurality of codes by a maximum value within an adjustable range for each of a plurality of cycles in a first section, the first section including a time frame from a time at which adjustment of a first code among the plurality of codes starts to a time at which the adjustment of the first code is completed to activate a first code adjustment completion signal;
• a multiplexer configured to selectively output the plurality of code adjustment clock signals and a plurality of duty detection valid signals according to the first code adjustment completion signal;
• a first code adjustment circuit configured to vary the first code according to the plurality of duty detection valid signals, and configured to generate a first code minimum detection signal and a first code maximum detection signal according to the first code;
• and
• a second code adjustment circuit configured to vary the second code according to an output of the multiplexer.