Duty-cycle error correction and reference spur reduction techniques for plls with reference frequency-doublers

An apparatus comprising:

• a squaring buffer circuit, the squaring buffer circuit including,
• a first inverter having a first inverter input coupled to a low edge rate input signal and a first inverter output supplying a square wave signal, the first inverter including a programmable portion;
• a bias circuit to provide a bias voltage to the first inverter input, the bias circuit including,
• a second inverter having a second inverter input shorted to a second inverter output, the second inverter being a scaled version of a fixed portion of the first inverter;
• a resistor coupled between the second inverter output and the first inverter input;
• a frequency doubler circuit coupled to the square wave signal and configured to supply a frequency doubled signal;
• and
• a phase-locked loop coupled to the frequency doubled signal, the phase-locked loop including,
• a phase detector coupled to the frequency doubled signal and to a feedback divider signal;
• a loop filter coupled to the phase detector;
• an oscillator coupled to the loop filter and configured to supply an oscillator output signal;
• a feedback divider coupled to the oscillator output signal and configured to supply the feedback divider signal;
• a duty cycle error correction circuit coupled to the square wave signal and wherein the duty cycle error correction circuit is responsive to a duty cycle error to adjust one or more duty cycle adjust signals to adjust PMOS or NMOS strength of the first inverter to reduce the duty cycle error;
• and
• wherein the duty cycle error correction circuit is configured to adjust the one or more duty cycle adjust signals based, at least in part, on a value of the square wave signal.