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US 2026/0301848 A1Published application
Data Output Path for a Memory with Double Redundancy
AssigneeQUALCOMM Incorporated
InventorsDebarghya DUTTA, Kiran DHAMANE, Rahul SAHU, Naresh GANDHAM, Akshdeepika LNU
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Abstract
A memory with double redundancy includes a plurality of global input/output columns each including a data output latch preceding a switch matrix. Each switch matrix is controlled by a corresponding decoder in an address decoding path including a master-slave latch controlled by a memory clock signal and another latch controlled by a sense amplifier enable signal.
Claims20
A memory, comprising:
- a first global input/output column including a first data output latch having a first output terminal;
- a second global input/output column including a second data output latch having a second output terminal;
- a third global input/output column including a third data output latch having a third output terminal;
- a first address latch configured to latch an address signal responsive to a memory clock signal to provide a first latched address signal;
- a second address latch configured to latch the first latched address signal responsive to a sense amplifier enable signal to provide a second latched address signal;
- a decoder configured to decode the second latched address signal to provide a decoded address signal;
- and
- a switch matrix configured to couple a selected one of the first output terminal, the second output terminal, and the third output terminal to a switch matrix output terminal responsive to the decoded address signal.
5 more elements
A method of column redundancy for a memory, comprising;
- latching a first address signal in a first latch responsive to a memory clock signal to provide a first latched address signal;
- latching the first latched address signal in a second latch responsive to a sense amplifier enable signal to provide a second latched address signal;
- decoding the second latched address signal to provide a decoded address signal;
- and
- selecting a latched data output signal from one of three consecutive columns responsive to the decoded address signal.
2 more elements
An address decoding path for a memory with double column redundancy, comprising:
- a first latch configured to latch an address signal responsive to a memory clock signal to provide a first latched address signal;
- a second latch configured to latch the first latched address signal responsive to a sense amplifier enable signal to provide a second latched address signal;
- and
- a decoder configured to decode the second latched address signal to provide a decoded address signal for controlling a selection of a latched data output from a selected one of three consecutive columns in the memory.
1 more element
Dependencies are inferred from the claim text.