Enhanced error correction code for error detection and correction in multi-level cell-based memory devices

An error correction code (ECC) decoder hardware device, comprising:

• error correction hardware circuitry;
• and
• error detection hardware circuitry communicably coupled to the error correction hardware circuitry, the error detection hardware circuitry to:
• receive data encoded with ECC information from a multi-level cell-based memory device;
• determine, by ECC error detection circuitry of the ECC decoder, an error type of the error, wherein the error type comprises one of no error, a single symbol error in the data, or multiple symbol errors in the data based at least in part on a +1/−1 error constraint;
• and
• responsive to the error type comprising multiple symbol errors, causing a repeat a read of the data from the multi-level cell-based memory device.

A system comprising:

• a multi-level cell-based memory device comprising a plurality of memory cells configured to store more than a single bit of data;
• an error correction code (ECC) encoding device to encode input data with ECC data to generated encoded data to transmit to the multi-level cell-based memory device;
• and
• an ECC decoding device to:
• receive data encoded with ECC information from a multi-level cell-based memory device;
• determine, by ECC error detection circuitry of the ECC decoder, an error type of the error, wherein the error type comprises one of no error, a single symbol error in the data, or multiple symbol errors in the data based at least in part on a +1/−1 error constraint;
• and
• responsive to the error type comprising multiple symbol errors, causing a repeat a read of the data from the multi-level cell-based memory device.