Voltage scaling based on error rate fluctuations
AssigneeMicron Technology, Inc.
InventorsLeon Zlotnik, Leonid Minz
Life of this patent
Estimating the term…
Abstract
A method includes determining a target total bit-error-rate (BER), calculating a target channel BER based on the target total BER, and training a channel to the calculated target channel BER by transmitting data over the channel in a loop from a physical input/output (PHY I/O) to a memory device, transmitting the test data over the channel in the loop from the memory device to the PHY I/O, wherein the data is looped from the memory device and back to the PHY I/O without being written to or road from the memory device, determining an actual channel BER based on the data transmitted to and received from the memory device, comparing the actual channel BER to the calculated target channel BER, and regulating a voltage value based on the comparison.
Claims20
An apparatus, comprising:
- a memory device;
- and
- a controller coupled to the memory device via an interface comprising a first physical input/output (PHY I/O) component and a second PHY I/O component;
- wherein the controller is configured to:
- send data to the memory device via the interface;
- and
- receive the data from the memory device via the interface;
- and
- determine an actual channel bit-error-rate (BER) based on the data sent to the memory device and the data received from the memory device;
- and
- regulate a voltage supplied to the first PHY I/O component based on a difference between the actual channel BER and a target channel BER.
A method, comprising:
- determining a target total bit-error-rate (BER) associated with transmitting data in a memory sub-system comprising a memory device and a controller;
- determining a target channel BER associated with transmitting data between a physical input/output (PHY I/O) component of the memory device and a PHY I/O component of the controller;
- and
- training a channel to the target channel BER by:
- transmitting data, over the channel in a loop between the PHY I/O component of the memory device and the PHY I/O component of the controller;
- determining an actual channel BER based on the data transmitted between the PHY I/O component of the memory device and the PHY I/O component of the controller;
- comparing the actual channel BER to the determined target channel BER;
- and
- regulating a voltage supplied to the PHY I/O component of the controller based on the comparison between the actual channel BER and the determined target channel BER.
An apparatus, comprising:
- a first physical input/output (PHY I/O) component of an interface between a controller and a memory device and corresponding to a channel;
- a second PHY I/O component of the interface;
- and
- wherein the controller is configured to:
- transmit data to the memory device via a channel;
- receive the data from the memory device via the channel;
- and
- determine an actual bit-error-rate (BER) corresponding to the channel based on the data transmitted between the memory device and the controller, wherein the actual BER corresponding to the channel is determined based on a difference between a total actual BER and a determined actual BER corresponding to the memory device;
- and
- regulate a voltage supplied to the first PHY I/O component based on a difference between the determined actual BER corresponding to the channel and a target BER corresponding to the channel.
Dependencies are inferred from the claim text.