Failure bits detection circuit, failure bits detection circuit method, and memory device

A failure bits detection method, comprising:

• mirroring a sensing current at a first end of a current mirror to generate a criteria current at a second end of the current mirror during a read mode of a memory device, wherein the first end of the current mirror is coupled to a page buffer of the memory device and the second end of the current mirror is coupled to a criteria generator;
• providing a criteria load between the second end of the current mirror and a reference ground end according to a criteria code;
• and
• comparing a first voltage at a first input end of a comparator with a second voltage at a second input end of the comparator to generate a detection result for determining a failure bits number of the memory device.

A memory device, comprising:

• a plurality of segments of memory cells, wherein each of the plurality of segments comprises a page buffer;
• and
• a plurality of failure bits detection circuits, wherein each of the plurality of failure bits detection circuits is coupled to the page buffer, respectively, and comprises:
• a current mirror, comprising a first end coupled to the page buffer of a memory device and a second end coupled to a criteria generator, and configured to:
• mirror a sensing current at the first end of the current mirror to generate a criteria current at the second end of the current mirror during the read mode of the memory device;
• and
• the criteria generator, configured to:
• provide a criteria load between the second end of the current mirror and a reference ground end according to a criteria code;
• and
• a comparator, comprising a first input end coupled to the first end of the current mirror, a second input end coupled to the second end of the current mirror, and an output end, and configured to:
• compare a first voltage at the first input end with a second voltage at the second input end to generate a detection result at the output end for determining a failure bits number of the memory device.