Memory device and storage device including the memory device

A memory device comprising:

• a memory cell array including a first memory cell and a third memory cell coupled to a first bit line extending in a first direction, and a second memory cell and a fourth memory cell coupled to a second bit line extending in the first direction, the first memory cell and the second memory cell coupled to a first word line extending in a second direction perpendicular to the first direction, the third memory cell and the fourth memory cell coupled to a second word line extending in the second direction;
• a peripheral circuit including a first page buffer coupled to the first memory cell and the third memory cell via the first bit line, and a second page buffer coupled to the second memory cell and the fourth memory cell via the second bit line;
• and
• a control logic circuit configured to control the peripheral circuit;
• wherein the second memory cell and the fourth memory cell are positioned farther from a first reference position in the second direction than the first memory cell and the third memory cell are positioned relative to the first reference position in the second direction;
• wherein the first memory cell and the second memory cell are positioned farther from a second reference position in the first direction than the third memory cell and the fourth memory cell are positioned relative to the second reference position in the first direction;
• and
• wherein the first page buffer and the second page buffer are configured to perform one of a sensing operation and a double-verify program operation on the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell during one of a plurality of time periods, each time period having a different length.

A storage device comprising:

• a memory device configured to perform a read operation and a program operation;
• and
• a memory controller configured to control the memory device;
• wherein the memory device comprises:
• a memory cell array including a first memory cell coupled to first bit line extending in a first direction and a second memory cell coupled to a second bit line extending in the first direction;
• a peripheral circuit including a first page buffer coupled to the first memory cell via the first bit line and a second page buffer coupled to the second memory cell via the second bit line;
• and
• a control logic circuit configured to control the peripheral circuit;
• wherein the second memory cell is positioned farther from a reference position in a second direction perpendicular to the first direction than the first memory cell is positioned relative to the reference position in the second direction;
• and
• wherein the first page buffer and the second page buffer are configured to perform one of a sensing operation and a double-verify program operation on the first memory cell and the second memory cell during one of a plurality of time periods, each time period having a different length.