Semiconductor memory device, memory system, and control method

A semiconductor memory device comprising:

• a plurality of memory cell transistors;
• and
• a control circuit configured to set a threshold voltage of each of the memory cell transistors to be in one of a plurality of voltage ranges separate from each other to store multi-bit data in each of the memory cell transistors, the plurality of voltage ranges including a first voltage range corresponding to a first multi-bit value, a second voltage range that is lower than the first voltage range and corresponds to a second multi-bit value, and a third voltage range that is the lowest in the plurality of voltage ranges and corresponds to an erased state, wherein
• when a target memory cell transistor in which data of the second multi-bit value is to be written currently stores data of the first multi-bit value, the control circuit is configured to apply a first voltage to a gate of the target memory cell transistor, to shift the threshold voltage of the target memory cell transistor to be in the second voltage range without dropping into the third voltage range.