Program operations in memory devices

A memory device, comprising:

• a memory cell array;
• and
• a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
• performing, based on one of 2N pieces of N-bits data to be stored in a target memory cell in the memory cell array, a first programming operation of the target memory cell to program the target memory cell into an intermediate threshold voltage range
• P
• 1
• I
• of a first set of 2N-1 threshold voltage ranges
• {
• P
• 1
• 0
• ,
• P
• 1
• 1
• ,
• …
• ,
• P
• 1
• 2
• N
• -
• 2
• }
• ,
• wherein N is an integer greater than 1, and a highest threshold voltage range
• P
• 1
• 2
• N
• -
• 2
• and a second-highest threshold voltage range
• P
• 1
• 2
• N
• -
• 3
• of the first set of 2N-1 threshold voltage ranges share a same verify voltage;
• and
• performing, based on the one of 2N pieces of N-bits data and the intermediate threshold voltage range
• P
• 1
• I
• ,
• a second programming operation of the target memory cell to program the target memory cell into one of a second set of 2N threshold voltage ranges
• {
• P
• 2
• 0
• ,
• P
• 2
• 1
• ,
• …
• ,
• P
• 2
• 2
• N
• -
• 1
• }
• ,
• herein the second set of 2N threshold voltage ranges
• {
• P
• 2
• 0
• ,
• P
• 2
• 1
• ,
• …
• ,
• P
• 2
• 2
• N
• -
• 1
• }
• correspond to the 2N pieces of N-bits data respectively.

A memory system, comprising:

• a memory device, comprising:
• a memory cell array;
• and
• a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
• performing, based on one of 2N pieces of N-bits data to be stored in a target memory cell in the memory cell array, a first programming operation of the target memory cell to program the target memory cell into an intermediate threshold voltage range
• P
• 1
• I
• of a first set of 2N-1 threshold voltage ranges
• {
• P
• 1
• 0
• ,
• P
• 1
• 1
• ,
• …
• ,
• P
• 1
• 2
• N
• -
• 2
• }
• ,
• wherein N is an integer greater than 1, and a highest threshold voltage range
• P
• 1
• 2
• N
• -
• 2
• and a second-highest threshold voltage range
• P
• 1
• 2
• N
• -
• 3
• of the first set of 2N-1 threshold voltage ranges share a same verify voltage;
• and
• performing, based on the one of 2N pieces of N-bits data and the intermediate threshold voltage range
• P
• 1
• I
• ,
• a second programming operation of the target memory cell to program the target memory cell into one of a second set of 2N threshold voltage ranges
• {
• P
• 2
• 0
• ,
• P
• 2
• 1
• ,
• …
• ,
• P
• 2
• 2
• N
• -
• 1
• }
• ,
• wherein the second set of 2N threshold voltage ranges,
• {
• P
• 2
• 0
• ,
• P
• 2
• 1
• ,
• …
• ,
• P
• 2
• 2
• N
• -
• 1
• }
• correspond to the 2N pieces of N-bits data respectively;
• and
• a controller coupled to the memory device and configured to send one or more signals to the memory device to initiate the operations.