Wordline pass through voltage management during a programming operation
AssigneeMicron Technology, Inc.
InventorsVinh Quang Diep, Ching-Huang Lu, Yingda Dong
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Abstract
A memory device includes a memory array and control logic operatively coupled with the memory array. The control logic performs operations comprising causing, prior to application of a programming pulse of a programming operation to a target wordline of the memory array, a pass through voltage to be applied to a portion of a set of drain-side wordlines of the memory device. The control logic further causes, during application of a target programming voltage level to the target wordline, a ramping down of the pass through voltage applied to the portion of the set of drain-side wordlines to a default pass through voltage.
Claims20
A memory device comprising:
- a memory array;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- causing, prior to application of a programming pulse of a programming operation to a target wordline of the memory array, a pass through voltage to be applied to a portion of a set of drain-side wordlines of the memory device;
- and
- causing, during application of a target programming voltage level to the target wordline, a ramping down of the pass through voltage applied to the portion of the set of drain-side wordlines to a default pass through voltage.
A memory device comprising:
- a memory array;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- identifying a request to execute a programming operation to program a set of memory cells associated with a target wordline of the memory array;
- causing, prior to application of a programming pulse of the programming operation to the target wordline, a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device, wherein the first adjusted pass through voltage is a first default pass through voltage increased by a first delta voltage level;
- causing, prior to the application of the programming pulse of the programming operation to the target wordline, a second adjusted pass through voltage to be applied to a set of source-side wordlines of the memory device, wherein the second adjusted pass through voltage is a second default pass through voltage decreased by a second delta voltage level, such that the first adjusted pass through voltage is greater than the second adjusted pass through voltage;
- and
- causing, during application of a target programming voltage level to the target wordline, a ramping down of the first adjusted pass through voltage applied to the first portion of the first set of drain-side wordlines to the first default pass through voltage and a ramping up of the second adjusted pass through voltage applied to the set of source-side wordlines to the second default pass through voltage, wherein the ramping down and the ramping up occur within a step-down time period that is less than a pulse time during which the target programming voltage level is applied to the target wordline.
A memory device comprising:
- a memory array;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- causing, prior to application of a programming pulse of a programming operation to a target wordline of the memory array, a first pass through voltage to be applied to a set of drain-side wordlines of the memory device and a second pass through voltage to be applied to a set of source-side wordlines of the memory device, wherein the first pass through voltage is greater than the second pass through voltage;
- and
- causing, during application of a target programming voltage level to the target wordline, a ramping down of the first pass through voltage applied to the set of drain-side wordlines and a ramping up of the second pass through voltage applied to the set of source-side wordlines.
Dependencies are inferred from the claim text.