Embedded memory device including cropped bitline structure and operating method thereof

An embedded memory device comprising:

• a bit cell array connected between a bitline and a complementary bitline;
• a cropping cell connected between the bitline and the complementary bitline;
• a global bitline connected to the bitline in a write operation;
• and
• a complementary global bitline connected to the complementary bitline in the write operation,
• wherein the global bitline is implemented as an upper metal member,
• wherein the bitline is implemented as a lower metal member disposed below the upper metal member, and
• wherein, after the write operation, a voltage of the bitline is maintained based on a voltage of the complementary global bitline, and a voltage of the complementary bitline is maintained based on a voltage of the global bitline.

An operating method of an embedded memory device including a plurality of bit cells connected between a local bitline and a complementary local bitline, the operating method comprising:

• electrically connecting the local bitline to a global bitline, and connecting the complementary local bitline to a complementary global bitline by using a cropping cell connected between the local bitline and the complementary local bitline;
• performing a write operation on a selected bit cell connected to the local bitline by applying a crop wordline signal having a first level to a crop wordline;
• and
• after performing the write operation, maintaining a voltage of the local bitline based on a voltage of the complementary global bitline, and maintaining a voltage of the complementary local bitline based on a voltage of the global bitline,
• wherein the global bitline is implemented as an upper metal member, and
• wherein the local bitline is implemented as a lower metal member disposed below the upper metal member.