US 2026/0301802 A1Published application

Stacked fet sram with top-layer pass-gate

AssigneeInternational Business Machines Corporation

InventorsChen Zhang, Junli Wang, Shay Reboh, Shahrukh Khan, Utkarsh Bajpai, Tenko Yamashita

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Abstract

Stacked field effect transistor (FET) static random access memory (SRAM) structures, circuits, and associated fabrication methods are presented. Recently there has been an emerging interest in considering stacked field effect transistor static random access memory bit-cell device designs that locate their pass-gate transistors on a top layer. This disclosure provides such designs. In particular, two x-couple implementations are presented that have their pass-gate transistors on a top layer. One implementation locates its x-couple between a top FET and a bottom FET. The other implementation locates its x-couple on the backside of the wafer.

Claims25

Dependent claims

A semiconductor structure, comprising:

a bottom device level including a first bottom field effect transistor (FET) of a first conductivity type, a second bottom FET of the first conductivity type, a third bottom FET of the first conductivity type, and a fourth bottom FET of the first conductivity type, wherein the first bottom FET is electrically connected to the second bottom FET and the third bottom FET is electrically connected to the fourth bottom FET, and the first bottom FET is located diagonally to the fourth bottom FET and the second bottom FET is located diagonally to the third bottom FET;
and
a top device level stacked above the bottom device level and including a first top FET of a second conductivity type different from the first conductivity type located directly above the first bottom FET, a second top FET of the second conductivity type located directly above the second bottom FET, a third top FET of the second conductivity type located directly above the third bottom FET, and a fourth top FET of the second conductivity type located directly above the fourth bottom FET, and the first top FET and the fourth top FET are pass gates,
wherein the first top FET is electrically connected to the second top FET and the third top FET is electrically connected to the fourth top FET, and the first bottom FET is a first dummy transistor which is wired to cross-couple with the third bottom FET and the fourth bottom FET is a second dummy transistor which is wired to cross-couple with the second bottom FET, and the second bottom FET and the second top FET are wired to provide a first inverter and the third bottom FET and the third top FET are wired to provide a second inverter.

1 more element

A semiconductor structure, comprising:

a bottom device level including a first bottom field effect transistor (FET) of a first conductivity type, a second bottom FET of the first conductivity type, a third bottom FET of the first conductivity type, and a fourth bottom FET of the first conductivity type, wherein the first bottom FET is electrically connected to the second bottom FET and the third bottom FET is electrically connected to the fourth bottom FET, and the first bottom FET is located diagonally to the fourth bottom FET and the second bottom FET is located diagonally to the third bottom FET;
and
a top device level stacked above the bottom device level and including a first top FET of a second conductivity type different from the first conductivity type located directly above the first bottom FET, a second top FET of the second conductivity type located directly above the second bottom FET, a third top FET of the second conductivity type located directly above the third bottom FET, and a fourth top FET of the second conductivity type located directly above the fourth bottom FET, and the first top FET and the fourth top FET are pass gates,
wherein the first top FET is electrically connected to the second top FET and the third top FET is electrically connected to the fourth top FET, and the first bottom FET is a first dummy transistor which is wired to cross-couple with the third bottom FET and the fourth bottom FET is a second dummy transistor which is wired to cross-couple with the second bottom FET, and the second bottom FET and the second top FET are wired to provide a first inverter and the third bottom FET and the third top FET are wired to provide a second inverter,
wherein a first middle level contact is conductively coupled to a gate of the third bottom FET, and
wherein the first middle level contact connects to both a gate of the first bottom FET and a first vertical S/D contact, forming a first middle level cross-couple.

3 more elements

A semiconductor structure, comprising:

a bottom device level including a first bottom field effect transistor (FET) of a first conductivity type, a second bottom FET of the first conductivity type, a third bottom FET of the first conductivity type, and a fourth bottom FET of the first conductivity type, wherein the first bottom FET is electrically connected to the second bottom FET and the third bottom FET is electrically connected to the fourth bottom FET, and the first bottom FET is located diagonally to the fourth bottom FET and the second bottom FET is located diagonally to the third bottom FET;
and
a top device level stacked above the bottom device level and including a first top FET of a second conductivity type different from the first conductivity type located directly above the first bottom FET, a second top FET of the second conductivity type located directly above the second bottom FET, a third top FET of the second conductivity type located directly above the third bottom FET, and a fourth top FET of the second conductivity type located directly above the fourth bottom FET, and the first top FET and the fourth top FET are pass gates,
wherein the first top FET is electrically connected to the second top FET and the third top FET is electrically connected to the fourth top FET, and the first bottom FET is a first dummy transistor which is wired to cross-couple with the third bottom FET and the fourth bottom FET is a second dummy transistor which is wired to cross-couple with the second bottom FET, and the second bottom FET and the second top FET are wired to provide a first inverter and the third bottom FET and the third top FET are wired to provide a second inverter,
wherein a first backside contact is conductively coupled to a gate of the third bottom FET, and
wherein the first backside contact connects to both a gate of the first bottom FET and a drain epi of the second bottom FET, forming a first backside cross-couple.

3 more elements

A semiconductor circuit, comprising:

a bottom circuit level including a first bottom field effect transistor (FET) of a first conductivity type, a second bottom FET of the first conductivity type, a third bottom FET of the first conductivity type, and a fourth bottom FET of the first conductivity type, wherein the first bottom FET is electrically connected to the second bottom FET and the third bottom FET is electrically connected to the fourth bottom FET, and the first bottom FET is located diagonally to the fourth bottom FET and the second bottom FET is located diagonally to the third bottom FET;
and
a top circuit level stacked above the bottom circuit level and including a first top FET of a second conductivity type different from the first conductivity type located directly above the first bottom FET, a second top FET of the second conductivity type located directly above the second bottom FET, a third top FET of the second conductivity type located directly above the third bottom FET, and a fourth top FET of the second conductivity type located directly above the fourth bottom FET, and the first top FET and the fourth top FET are pass gates,
wherein the first top FET is electrically connected to the second top FET and the third top FET is electrically connected to the fourth top FET, and the first bottom FET is a first dummy transistor which is wired to cross-couple with the third bottom FET and the fourth bottom FET is a second dummy transistor which is wired to cross-couple with the second bottom FET, and the second bottom FET and the second top FET are wired to provide a first inverter and the third bottom FET and the third top FET are wired to provide a second inverter.

1 more element

A semiconductor circuit, comprising:

a bottom circuit level including a first bottom field effect transistor (FET) of a first conductivity type, a second bottom FET of the first conductivity type, a third bottom FET of the first conductivity type, and a fourth bottom FET of the first conductivity type, wherein the first bottom FET is electrically connected to the second bottom FET and the third bottom FET is electrically connected to the fourth bottom FET, and the first bottom FET is located diagonally to the fourth bottom FET and the second bottom FET is located diagonally to the third bottom FET;
and
a top circuit level stacked above the bottom circuit level and including a first top FET of a second conductivity type different from the first conductivity type located directly above the first bottom FET, a second top FET of the second conductivity type located directly above the second bottom FET, a third top FET of the second conductivity type located directly above the third bottom FET, and a fourth top FET of the second conductivity type located directly above the fourth bottom FET, and the first top FET and the fourth top FET are pass gates,
wherein the first top FET is electrically connected to the second top FET and the third top FET is electrically connected to the fourth top FET, and the first bottom FET is a first dummy transistor which is wired to cross-couple with the third bottom FET and the fourth bottom FET is a second dummy transistor which is wired to cross-couple with the second bottom FET, and the second bottom FET and the second top FET are wired to provide a first inverter and the third bottom FET and the third top FET are wired to provide a second inverter,
wherein a first middle level contact is conductively coupled to a gate of the third bottom FET, and
wherein the first middle level contact connects to both a gate of the first bottom FET and a first vertical S/D contact, forming a first middle level cross-couple.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/093,517Filed 28 Mar 2025
Published: 1 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 11/412
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…
H10D 30/502
FETs having stacked nanowire, nanosheet or nanoribbon channels: characterised by the stacked channels