Memory system

A memory system comprising:

• a non-volatile memory including first and second blocks, each of the first and second blocks including first, second, third, and fourth strings, each of the first to fourth strings including a plurality of memory cells and a first select transistor electrically connected in series with the memory cells, the memory cells being connected in series, the memory cells including a first memory cell and a second memory cell, each of the first and second blocks including:
• a bit line electrically connected to the first to fourth strings;
• a first select gate line electrically connected to a gate of the first select transistor of the first string in the first block;
• a second select gate line electrically connected to a gate of the first select transistor of the second string in the first block;
• a third select gate line electrically connected to a gate of the first select transistor of the third string in the first block;
• a fourth select gate line electrically connected to a gate of the first select transistor of the fourth string in the first block;
• a first word line electrically connected to gates of the first memory cell of the first string in the first block, the first memory cell of the second string in the first block, the first memory cell of the third string in the first block, and the first memory cell of the fourth string in the first block;
• and
• a second word line electrically connected to gates of the second memory cell of the first string in the first block, the second memory cell of the second string in the first block, the second memory cell of the third string in the first block, and the second memory cell of the fourth string in the first block;
• and
• a memory controller configured to control the non-volatile memory, wherein
• the memory controller is configured to execute a first read process of reading data from the first memory cell of the first string in the first block, by using a first read voltage, and a second read process of reading data from a second memory cell of the first string in the first block, by using a second read voltage,
• the memory controller is configured to maintain, in a case that a first condition is satisfied, a difference between the first read voltage and the second read voltage at a first value, and change both the first read voltage and the second read voltage,
• the first condition is a first sub-condition, a second sub-condition, or a third sub-condition,
• the first sub-condition is that a first period elapses after data is written to the first memory cell and the second memory cell,
• the second sub-condition is that the memory controller executes the first read process independently of an instruction from an external host,
• the third sub-condition is that data including fail bits greater than or equal to a second threshold is read from the first block.